module mul_addtree(
clk,rst_n,mul_a,mul_b,mul_out
);
parameter MUL_WIDTH=4;
parameter MUL_RESULT=8;
input clk;
input rst_n;
input [MUL_WIDTH-1:0]mul_a;
input [MUL_WIDTH-1:0]mul_b;
output [MUL_RESULT-1:0]mul_out;
reg [MUL_RESULT-1:0]mul_out;
reg [MUL_RESULT-1:0]store0;
reg [MUL_RESULT-1:0]store1;
reg [MUL_RESULT-1:0]store2;
reg [MUL_RESULT-1:0]store3;
reg [MUL_RESULT-1:0]add01;
reg [MUL_RESULT-1:0]add23;
always @( posedge clk or negedge rst_n )
begin
if(!rst_n)
begin
mul_out<=8'b0000_0000;
store0<=8'b0000_0000;
store1<=8'b0000_0000;
store2<=8'b0000_0000;
store3<=8'b0000_0000;
add01<=8'b0000_0000;
add23<=8'b0000_0000;
end
else
begin
store0<=mul_b[0]?{4'b0000,mul_a}:8'b0000_0000;
store1<=mul_b[1]?{3'b000,mul_a,1'b0}:8'b0000_0000;
store2<=mul_b[2]?{2'b00,mul_a,2'b00}:8'b0000_0000;
store3<=mul_b[3]?{1'b0,mul_a,3'b000}:8'b0000_0000;
add01<=store0+store1;
add23<=store2+store3;
mul_out<=add01+add23;
end
end
endmodule