CRC16 编码器的Verilog HDL 实现

G(x) = x16 + x15 + x2 +1
module crc_16(
clk,rst,x,crc_reg,crc_s
    );
 input clk;
 input rst;
 input x;//serial input
 output [15:0]crc_reg;
 output crc_s;//the synchronous signal
 reg [15:0]crc_reg;
 reg [3:0]count;
 reg crc_s; 
 wire [15:0]crc_enc;
 always @( posedge clk)
 begin
if(!rst)
begin
crc_reg<=16'b0;
count<=4'b0;
end
else
begin
crc_reg<=crc_enc;
count<=count+1;
if(count==0)
crc_s<=0;//the low level synchronous enable signal
else
crc_s<=1;
end
 end
 assign crc_enc[0]=crc_reg[15]^x;
 assign crc_enc[1]=crc_reg[0];
 assign crc_enc[2]=crc_reg[1]^crc_reg[15]^x;
 assign crc_enc[14:3]=crc_reg[13:2];
 assign crc_enc[15]=crc_reg[15]^crc_reg[14]^x;
endmodule