基于FPGA的均值滤波（四）

reg [2*DW-1:0] mean_temp;
reg [2*DW-1:0] mean_temp1;
reg [2*DW-1:0] mean_temp2;
reg [2*DW-1:0] mean_temp3;
reg [2*DW-1:0] mean_temp4;
reg [2*DW-1:0] mean_temp5;
reg [2*DW-1:0] mean_temp6;
reg [2*DW-1:0] mean_temp7;
reg [2*DW-1:0] mean_temp8;
wire [DW-1:0] mean_temp9;
wire [DW+3-1:0] mean_temp10;
wire [2*DW+6-1:0] mean_temp11;
wire [2*DW-1:0] mean_out_temp;
generate
if(KSZ==5)
begin : divide_25
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
mean_temp <= {2*DW-1+1{1'b0}};
mean_temp1 <= {2*DW-1+1{1'b0}};
mean_temp2 <= {2*DW+1{1'b0}};
mean_temp3 <= {2*DW+5-1+1{1'b0}};
mean_temp4 <= {2*DW+6-1+1{1'b0}};
mean_temp5 <= {2*DW+1-1+1{1'b0}};
mean_temp6 <= {2*DW+6-1+1{1'b0}};
end
else
begin
//将二维求和结果缓存到mean_temp
if(sum_dout_valid[3])
mean_temp <= sum_dout_r[2];
//下一拍计算
if(sum_dout_valid[4])
begin
//计算mean_temp (2^-6+2^-7)
mean_temp1 <= ({6'b000000,mean_temp[2*DW-1:6]})+({7'b0000000,mean_temp[2*DW-1:7]});
//计算mean_temp (2^-3+2^-4)
mean_temp2 <= ({4'b0000,mean_temp[2*DW-1:4]})+({5'b00000,mean_temp[2*DW-1:5]});
//计算mean_temp (2^-1+2^-2)
mean_temp3 <= ({1'b0,mean_temp[2*DW-1:1]})+({2'b00,mean_temp[2*DW-1:2]});
//计算mean_temp (2^3+2^5)
mean_temp4 <= ({mean_temp[2*DW-4:0]},3'b000)+({mean_temp[2*DW-6:0]},5'b00000);
end
//下一排计算上一排的中间结果
if(sum_dout_valid[5])
begin
mean_temp5 <= mean_temp1 + mean_temp2;
mean_temp6 <= mean_temp3 + mean_temp4;
end
//下一排计算上一排的中间结果
if(sum_dout_valid[6])
mean_temp7<= mean_temp6 + mean_temp7;
end
end
endgenerate
//求和结果除以1024的结果
assign mean_temp8 = (sum_is_broarder_r[6]==1'b0)?(mean_temp7>>10):(2*DW{1'b0});
//四舍五入操作
assign mean_temp9 = (mean_temp[7] == 1'b1) ? (mean_temp8[DW-1:0]+1'b1):mean_temp8[DW-1:0];
//对输出结果保存三位小数‘
assign mean_temp11 = (sum_is_broarder_r[6]==1'b0) ? (mean_temp7>>7) : {2*DW-1-1{1'b0}};
assign mean_temp10 = (mean_temp11[DW+3-1:0] + 1'b1)