VHDL实现与门，或门，非门。

--二输入与门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY and2 IS
	PORT(a,b:IN STD_LOGIC;
		c:OUT STD_LOGIC);
END and2;
ARCHITECTURE and2_behavior OF and2 IS
BEGIN
	c<= a AND b;
END and2_behavior;

--二输入或门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2 IS
	PORT(a,b:IN STD_LOGIC;
		c:OUT STD_LOGIC);
END or2;
ARCHITECTURE or2_behavior OF or2 IS
BEGIN
	c<=a OR b;
END or2_behavior;

--非门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY not_gate IS
	PORT(a:IN STD_LOGIC;
		f:OUT STD_LOGIC);
END not_gate;
ARCHITECTURE not_gate_behavior OF not_gate IS
BEGIN
	f<= NOT a;
END not_gate_behavior;

--二输入与门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY and2 IS
	PORT(a,b:IN STD_LOGIC;
		c:OUT STD_LOGIC);
END and2;
ARCHITECTURE and2_behavior OF and2 IS
BEGIN
	PROCESS(a,b)
	VARIABLE comb:STD_LOGIC_VECTOR(0 TO 1);
	BEGIN
		comb:= a&b;
		CASE comb IS
			WHEN "00" => c<='0';
			WHEN "01" => c<='0';
			WHEN "10" => c<='0';
			WHEN "11" => c<='1';
                        WHEN OTHERS => c<='Z';
		END CASE;
	END PROCESS;
END and2_behavior;

--二输入或门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2 IS
	PORT(a,b:IN STD_LOGIC;
		c:OUT STD_LOGIC);
END or2;
ARCHITECTURE or2_behavior OF or2 IS
SIGNAL comb:STD_LOGIC_VECTOR(0 TO 1);
BEGIN
	comb<= a&b;
	WITH comb SELECT
	c<= '0' WHEN "00",
		'1' WHEN "01",
		'1' WHEN "10",
		'1' WHEN "11";
		'z' WHEN OTHERS;
END or2_behavior;

--非门
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY not_gate IS
	PORT(a:IN STD_LOGIC;
		f:OUT STD_LOGIC);
END not_gate;
ARCHITECTURE not_gate_behavior OF not_gate IS
BEGIN
	f<= '0' WHEN a='1' ELSE
		'1' WHEN a='0' ELSE
		'Z';
END not_gate_behavior;