VHDL实现加法器的设计

LIBRARY IEEE;
LIBRARY IEEE.STD_LOGIC_1164.ALL;
ENTITY half_add_1 IS
	PORT(a:IN STD_LOGIC;
		b:IN STD_LOGIC;
		co:OUT STD_LOGIC;
		s:OUT STD_LOGIC);
END half_add_1;
ARCHITECTURE half_add_1_behavior OF half_add_1 IS
BEGIN
	co<= a AND b;
	s<= a XOR b;
END half_add_1_behavior;

--1位全加器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_add_1 IS
	PORT(a,b,cin:IN STD_LOGIC;
		co,sum:OUT STD_LOGIC);
END full_add_1;
ARCHITECTURE full_add_1_behavior OF full_add_1 IS
	COMPONENT half_add_1
	PORT(a:IN STD_LOGIC;
		b:IN STD_LOGIC;
		co:OUT STD_LOGIC;
		s:OUT STD_LOGIC);
	END COMPONENT;
	SIGNAL temp1,temp2,temp3:STD_LOGIC;
	BEGIN
	u1:half_add_1 PORT MAP(a,b,temp1,temp2);
	u2:half_add_1 PORT MAP(temp1,cin,temp3,s);
	co<=temp1 OR temp3;
END full_add_1_behavior;