[十六]Cracking Digital VLSI Verification Interview

class rw_txn extends uvm_sequence_item;
    
    rand bit[7:0] addr; //address of transaction
    typedef enum {READ, WRITE} kind_e; //read or write type
    rand kind_e sram_cmd;
    rand bit[7:0] datain; //data
    
    //Register with factory for dynamic creation
    `uvm_object_utils(rw_txn)
    
    //constructor
    function new (string name = "rw_txn");
        super.new(name);
    endfunction
    
    //Print utility
    function string convert2string();
        return $psprintf("sram_cmd=%s addr=%0h datain=%0h,sram_cmd.name(),addr,datain);
    endfunction
                         
endclass

class sram_sequence extends uvm_sequence#(rw_txn) ; //Register with factory
    
    `uvm_object_utils(sram_sequence)
    
    function new(string name ="sram_sequence");
        super.new(name);
    endfunction
    
    //Main Body method that gets executed once sequence is started
    task body();
        rw_txn rw_trans; //Create 10 random SRAM read/write transaction and send to driver 
        repeat(10) begin
            rw_trans = rw_txn::type_id::create(.name("rw_trans"),.contxt(get_full_name())); 
            start_item(rw_trans); //start arbitration to sequence
            assert (rw_trans.randomize());//randomize item
            finish_item(rw_trans); //send to driver
        end
    endtask
    
endclass

class sram_driver extends uvm_driver#(rw_txn);
    `uvm_component_utils(sram_driver) 
    virtual sram_if vif; //Interface that groups dut signals
    function new(string name,uvm_component parent = null);
        super.new(name,parent);
    endfunction
    
    //Build Phase
    
    //Get the virtual interface handle from config_db
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        if (!uvm_config_db#(virtual sram_if)::get(this, "", "sram_if", vif))
            begin
                `uvm_fatal("SRAM/DRV", "No virtual interface specified")
            end
    endfunction
    
    //Run Phase
    
    //Implement the Driver-Sequencer API to get an item
    //Based on if it is Read/Write - drive on SRAM interface the corresponding pins virtual 
    task run_phase(uvm_phase phase);
        super.run_phase(phase);
        this.vif.read_enable <= '0;
        this.vif.write_enable <= '0;
        forever begin
            rw_txn tr;
            @ (this.vif.master_cb);
            //First get an item from sequencer
            seq_item_port.get_next_item(tr);
            @ (this.vif.master_cb); //wait for a clock edge
            uvm_report_info("SRAM_DRIVER ", $psprintf("Got Transaction%s",tr.convert2string()));
            //Decode the SRAM Command and call either the read/write function 
            case (tr.sram_cmd)
                rw_txn::READ: drive_read(tr.addr, tr.dataout);
                rw_txn::WRITE: drive_write(tr.addr, tr.datain);
            endcase
            //Handshake DONE back to sequencer
            seq_item_port.item_done();
        end
     endtask: run_phase
                                                      
//Drive the SRAM signals needed for a Read
     virtual protected task drive_read(input bit [31:0] addr, output logic [31:0] data);
         this.vif.master_cb.addr <= addr;
         this.vif.master_cb.write_enable <= '0; 
         this.vif.master_cb.read_enable <= '1;
         @ (this.vif.master_cb);
         this.vif.master_cb.read_enable <= '0; 
         data = this.vif.master_cb.dataout;
     endtask: drive_read
                                                      
//Drive the SRAM signals needed for a Write
     virtual protected task drive_write(input bit [31:0] addr, input bit [31:0] data);
         this.vif.master_cb.addr <= addr; 
         this.vif.master_cb.write_enable <= '1; 
         this.vif.master_cb.read_enable <= '0;
         @ (this.vif.master_cb);
         this.vif.master_cb.write_enable <= '0;
     endtask: drive_write
endclass

class test_seq_c extends uvm_sequence;
    `uvm_object_utils(test_seq_c)
    
class test_driver_c extends uvm_component;
    `uvm_component_utils(test_driver_c)

task run_phase( uvm_phase phase);
    phase.raise_objection( this );
    my_test_sequence.start(my_sequencer);
    phase.drop_objection( this );
endtask

module test;
    initial begin
        set_global_timeout(1000ns);
    end
    
    initial begin
        run_test();
    end
endmodule

uvm_config_db#(<type>)::set(uvm_component context, string inst_name, string field_name,<type> value)
uvm_config_db#(<type>)::get(uvm_component context, string inst_name, string field_name, ref value)

module test;
    logic pclk;
    logic [31:0] paddr;
    
    //Instantiate an APB bus master DUT
    apb_master apb_master(.pclk(pclk),*); 
    
    //Instantiate a physical interface for APB interface
    apb_if apb_if(.pclk(pclk), *); 
    
    initial begin //Pass this physical interface to test class top //which will further pass it down to env->agent->drv/sqr/mon
        uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top", "vif",apb_if); 
    end 

endmodule

class apb_env extends uvm_env;
    `uvm_component_utils(apb_env); 
    
    //ENV class will have agent as its sub component
    apb_agent agt;
    
    //virtual interface for APB interface
    
    virtual apb_if vif; //Build phase - Construct agent and get virtual interface handle fromtest and pass it down to agent
    
    function void build_phase(uvm_phase phase);
        agt = apb_agent::type_id::create("agt", this);
        if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))begin 
            `uvm_fatal("config_db_err", "No virtual interface specified forthis env instance") 
        end 
        uvm_config_db#(virtual apb_if)::set( this, "agt", "vif", vif); 
    endfunction: build_phase 

endclass : apb_env