FPGA基础知识极简教程（6）UART通信与移位寄存器的应用

`timescale 1ns / 1ps
module baud_gen(
	input clk,
	input enable,
	output BaudTick
    );

	reg BaudTick_mid = 0;
	assign BaudTick = BaudTick_mid;
	reg [4:0] baud_count = 0;
	
	always@(posedge clk) begin
		if(enable) begin
			if(baud_count < 16) begin
				baud_count <= baud_count + 1;
				BaudTick_mid <= 0;
			end
			else if(baud_count == 16) begin
				baud_count <= 0;
				BaudTick_mid <= 1;
			end
			else ;		
		end
		else begin
			baud_count <= 0;
			BaudTick_mid <= 0;
		end	
	end		
endmodule

`timescale 1ns / 1ps
module baud_gen_tb(
    );

	
	reg enable;
	reg clk;
	wire Baud_Tick;
	
	initial begin
		clk = 0;
		forever 
			# 250 clk = ~clk;
	
	end
	initial enable = 1;
	
	baud_gen u0(
	.clk(clk),
	.enable(enable),
	.BaudTick(Baud_Tick)
	);
	

endmodule

`timescale 1ns / 1ps
module uart_tran(
	//input 
	input clk,
	input rst_n,
	input [7:0] data_in, //data needed to be transmitted
	input trig, //transmit data when the posedge trig

	//output
	output busy, //busy is asserted when the data is transmitting
	output reg tx //output serial data


    );
	parameter IDLE = 0, START_BIT = 1, BIT1 = 2, BIT2 = 3, BIT3 = 4, BIT4 = 5;

	parameter BIT5 = 6, BIT6 = 7, BIT7 = 8, BIT8 = 9, POLARITY = 10, STOP_BIT = 11;

	wire BaudTick;

	reg trig_r, trig_posedge;
	//get the posedge of the trig
	always@(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			trig_r <= 0;
			trig_posedge <= 0;
		end
		else begin
			trig_r <= trig;
			trig_posedge <= (~trig_r)&trig;
		end
	end

	//generate odd or even polarity bit
	wire odd_bit;   //奇校验位 = ~偶校验位
	wire even_bit;  //偶校验位 = 各位异或
	wire polarity_bit = even_bit;  //偶校验
	// wire POLARITY_BIT = odd_bit;   //奇校验

	assign even_bit = ^data_in; //even_bit = data_in[0] ^ data_in[1] ^ .....
	assign odd_bit = ~even_bit;

	assign busy = (cur_state == IDLE) ? 0 : 1 ; //busy is dessertted when the current state is IDLE

	// reg [10 : 0] data_in_buf;
	// always @ (posedge clk)
	// begin
 //   		if(!rst_n)
 //       		data_in_buf <= 11'b0;
 //   		else if(trig_posedge & (~busy))    //只读取一次数据，一帧数据发送过程中，改变输入无效
 //      		data_in_buf <= {1'b1, polarity_bit, data_in[7:0], 1'b0};   //数据帧拼接
	// end



	//state variable define
	reg [3:0] cur_state, nxt_state = IDLE;
	always@(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			cur_state <= IDLE;
		end
		else begin
			cur_state <= nxt_state;
		end
	end

	always@(*) begin
		case(cur_state)
			IDLE: begin
				if(trig_posedge) nxt_state = START_BIT;
			end
			START_BIT: begin
				if(BaudTick) nxt_state = BIT1;
			end
			BIT1: begin
				if(BaudTick) nxt_state = BIT2;
			end
			BIT2: begin
				if(BaudTick) nxt_state = BIT3;
			end
			BIT3: begin
				if(BaudTick) nxt_state = BIT4;
			end
			BIT4: begin
				if(BaudTick) nxt_state = BIT5;
			end
			BIT5: begin
				if(BaudTick) nxt_state = BIT6;
			end
			BIT6: begin
				if(BaudTick) nxt_state = BIT7;
			end
			BIT7: begin
				if(BaudTick) nxt_state = BIT8;
			end
			BIT8: begin
				if(BaudTick) nxt_state = POLARITY;
			end
			POLARITY: begin
				if(BaudTick) nxt_state = STOP_BIT;
			end
			STOP_BIT: begin
				if(BaudTick) nxt_state = IDLE;
			end
			default: begin
				if(BaudTick) nxt_state = IDLE;
			end
		endcase
	end

	reg tx_mid = 1;
	always@(*) begin
		case(cur_state)
			IDLE: begin
				if(trig_posedge) tx_mid = 1;
			end
			START_BIT: begin
				if(BaudTick) tx_mid = 0;
			end
			BIT1: begin
				if(BaudTick) tx_mid = data_in[0];
			end
			BIT2: begin
				if(BaudTick) tx_mid = data_in[1];
			end
			BIT3: begin
				if(BaudTick) tx_mid = data_in[2];
			end
			BIT4: begin
				if(BaudTick) tx_mid = data_in[3];
			end
			BIT5: begin
				if(BaudTick) tx_mid = data_in[4];
			end
			BIT6: begin
				if(BaudTick) tx_mid = data_in[5];
			end
			BIT7: begin
				if(BaudTick) tx_mid = data_in[6];
			end
			BIT8: begin
				if(BaudTick) tx_mid = data_in[7];
			end
			POLARITY: begin
				if(BaudTick) tx_mid = polarity_bit;
			end
			STOP_BIT: begin
				if(BaudTick) tx_mid = 1;
			end
			default: begin
				if(BaudTick) tx_mid = 1;
			end
		endcase
	end


	always@(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			tx <= 1;
		end
		else begin
			tx <= tx_mid;
		end
	end


	baud_gen inst_baud_gen(
		.clk(clk),
		.enable(1),
		.BaudTick(BaudTick)
		);

endmodule

`timescale 1ns / 1ps
module uart_tran_tb(
    );

	
	//input 
	reg clk;
	reg rst_n;
	reg [7:0] data_in; //data needed to be transmitted
	reg trig; //transmit data when the posedge trig

	//output
	wire busy; //busy is asserted when the data is transmitting
	wire tx;//output serial data
	
	initial begin
		clk = 0;
		forever 
			# 250 clk = ~clk;
	
	end

	initial begin
		rst_n = 0;
		trig = 0;
		#1000 rst_n = 1;
		trig = 1;
		data_in = 8'b1011_0011;
		#1000
		@(negedge clk) trig = 0;

	end



	
	uart_tran inst_uart_tran(
		.clk(clk),
		.rst_n(rst_n),
		.data_in(data_in),
		.trig(trig),
		.busy(busy),
		.tx(tx)
		);
	

endmodule

`timescale 1ns / 1ps
/////////////////////////////////////
// Engineer: Reborn Lee
/////////////////////////////////////


module uart_rec(
	input clk,
	input rst_n,
	input rx,
	output reg [7:0] rx_data_out,
	output reg rx_data_out_ready,
	output reg err_check,
	output reg err_frame

    );

	wire odd_bit;   //奇校验位 = ~偶校验位
	wire even_bit;  //偶校验位 = 各位异或
	wire POLARITY_BIT;   //本地计算的奇偶校验

	assign even_bit = ^rx_data_out;     //一元约简，= data_in[0] ^ data_in[1] ^ .....
	assign odd_bit = ~even_bit;
	assign POLARITY_BIT = even_bit;  //偶校验



	// the negedge of rx
	reg rx_r, rx_rr, rx_negedge;
	always@(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			rx_r <= 1;
			rx_rr <= 1;
			rx_negedge <= 0;
		end
		else begin
			rx_r <= rx;
			rx_rr <= rx_r;
			rx_negedge <= rx_r&(~rx);
		end
	end

	reg receive;
	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			// reset
			receive <= 0;
		end
		else if (rx_negedge) begin
			receive <= 1;
		end
		else if(rx_state == 4'b0010 && sampleNow) begin
			receive <= 0;
		end
		else begin
			;
		end
	end


	reg [4:0] OversamplingCnt = 0;

	always @(posedge clk) begin
		// OversamplingCnt <= (receive == 0) ? 1'd0 : OversamplingCnt + 1'd1;
		OversamplingCnt <= (receive == 1 && OversamplingCnt <= 15) ? OversamplingCnt + 1 : 0;
	end
		
		
	wire sampleNow = OversamplingCnt == 8;

	reg [3:0] rx_state = 4'b0000;
	always @(posedge clk)
		case(rx_state)
			4'b0000: if(receive) begin
						rx_state <= 4'b0001;  
					 end
			4'b0001: if(sampleNow) rx_state <= 4'b1000;  // sync start bit to sampleNow
			4'b1000: if(sampleNow) rx_state <= 4'b1001;  // bit 0
			4'b1001: if(sampleNow) rx_state <= 4'b1010;  // bit 1
			4'b1010: if(sampleNow) rx_state <= 4'b1011;  // bit 2
			4'b1011: if(sampleNow) rx_state <= 4'b1100;  // bit 3
			4'b1100: if(sampleNow) rx_state <= 4'b1101;  // bit 4
			4'b1101: if(sampleNow) rx_state <= 4'b1110;  // bit 5
			4'b1110: if(sampleNow) rx_state <= 4'b1111;  // bit 6
			4'b1111: if(sampleNow) rx_state <= 4'b0100;  // bit 7
			4'b0100: if(sampleNow) rx_state <= 4'b0010;  // polarity bit
			4'b0010: if(sampleNow) rx_state <= 4'b0000;  // stop bit
			default: rx_state <= 4'b0000;
		endcase


	always @(posedge clk)
		if(sampleNow && rx_state[3]) rx_data_out <= {rx_rr, rx_data_out[7:1]};

	always @(posedge clk) begin
		rx_data_out_ready <= (sampleNow && rx_state==4'b0100);  // make sure a stop bit is received
	end


//校验错误:奇偶校验不一致
always @ (posedge clk)
begin
    if(!rst_n)
        err_check <= 0;
    else if(rx_state == 4'b0100 && sampleNow)
    begin
        if(POLARITY_BIT != rx_rr)      //奇偶校验正确
            err_check <= 1;         //锁存     
    end
end

//帧错误:停止位不为1
always @ (posedge clk)
begin
    if(!rst_n)
        err_frame <= 0;
    else if(rx_state == 4'b0010 && sampleNow)
    begin
        if(rx_rr != 1)        //停止位
            err_frame <= 1;
    end
end
endmodule

	// the negedge of rx
	reg rx_r, rx_rr, rx_negedge;
	always@(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			rx_r <= 1;
			rx_rr <= 1;
			rx_negedge <= 0;
		end
		else begin
			rx_r <= rx;
			rx_rr <= rx_r;
			rx_negedge <= rx_r&(~rx);
		end
	end

reg receive;
	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			// reset
			receive <= 0;
		end
		else if (rx_negedge) begin
			receive <= 1;
		end
		else if(rx_state == 4'b0010 && sampleNow) begin
			receive <= 0;
		end
		else begin
			;
		end
	end

reg [4:0] OversamplingCnt = 0;

	always @(posedge clk) begin
		// OversamplingCnt <= (receive == 0) ? 1'd0 : OversamplingCnt + 1'd1;
		OversamplingCnt <= (receive == 1 && OversamplingCnt <= 15) ? OversamplingCnt + 1 : 0;
	end

`timescale 1ns / 1ps
 
module uart_rec_tb(
    );
	reg clk;
	reg rst_n;
	reg rx;
	wire [7:0] rx_data_out;
	wire rx_data_out_ready;
	wire err_check;
	wire err_frame;
 
	
	parameter DATA0 = 11'b11010101010; //从低位开始发送
	reg [10:0] data_in;
	
	initial begin
		clk = 0;
		forever 
			#250 clk = ~clk;
	end

	initial begin
		rst_n = 0;
		data_in = DATA0;
		rx = 1;
		#2000
		rst_n = 1;

		for(integer i = 0; i <= 10; i = i + 1) begin
			#8500
				rx = data_in[i];
		end
		
		#8680 rx = 1;
		#20000 $finish;
	
	end
	
	uart_rec inst_uart_sec(
		.clk(clk),
		.rst_n(rst_n),
		.rx(rx),
		.rx_data_out(rx_data_out),
		.rx_data_out_ready(rx_data_out_ready),
		.err_check(err_check),
		.err_frame(err_frame)
		);
	

endmodule

always @(posedge clk)
		if(sampleNow && rx_state[3]) rx_data_out <= {rx_rr, rx_data_out[7:1]};