基于FPGA的千兆以太网开发（3）

module ETH_TOP(
        input clk,   
        input rstn,
        output [7:0] led,
        
       // output  eth_reset_n2,
        output[3:0] rgmii_txd1,
        output rgmii_txctl1,
        output rgmii_txc1,
        input[3:0] rgmii_rxd1,
        input rgmii_rxctl1,
        input rgmii_rxc1
    );
    
//test-------------------------
assign rgmii_txd1 =rgmii_rxd1;
assign rgmii_txctl1=rgmii_rxctl1;
assign rgmii_txc1 =rgmii_rxc1;

ila_1 ila_1 (
	.clk(rgmii_rxc1), // input wire clk


	.probe0(rgmii_rxd1), // input wire [3:0]  probe0  
	.probe1(rgmii_rxctl1), // input wire [0:0]  probe1 
	.probe2(rgmii_txd1), // input wire [3:0]  probe2 
	.probe3(rgmii_txctl1) // input wire [0:0]  probe3
);
endmodlue

`timescale 1ns / 1ps  

module ethernet_test(
    input       sys_clk_50m,
    input       rst_n,

	output[3:0] rgmii_txd,
	output      rgmii_txctl,
	output      rgmii_txc,
	
	input[3:0]  rgmii_rxd,
	input       rgmii_rxctl,
	input       rgmii_rxc
    );
wire            reset_n;
(*mark_debug="true"*)wire   [ 7:0]   gmii_txd;
(*mark_debug="true"*)wire            gmii_tx_en;
(*mark_debug="true"*)wire            gmii_tx_er;
(*mark_debug="true"*)wire            gmii_tx_clk;
wire            gmii_crs;
wire            gmii_col;
(*mark_debug="true"*)wire   [ 7:0]   gmii_rxd;
(*mark_debug="true"*)wire            gmii_rx_dv;
(*mark_debug="true"*)wire            gmii_rx_er;
(*mark_debug="true"*)wire            gmii_rx_clk;
wire            duplex_mode;     // 1 full, 0 half
wire            rgmii_rxcpll;

wire  [31:0]    pack_total_len ;

wire [1:0]      speed      ;
wire            link       ;
wire            e_rx_dv    ;
wire [7:0]      e_rxd      ;
wire            e_tx_en    ;
wire [7:0]      e_txd      ;
wire            e_rst_n    ; 

 assign duplex_mode = 1'b1;
 assign speed= 2'b10;
 assign link='b1;
 

ila_0 ila_0 (
	.clk(rgmii_rxc), // input wire clk


	.probe0(rgmii_rxd), // input wire [7:0]  probe0  
	.probe1(rgmii_rxctl), // input wire [0:0]  probe1 
	.probe2(gmii_rxd), // input wire [7:0]  probe2 
	.probe3(gmii_rx_dv) // input wire [0:0]  probe3
);

util_gmii_to_rgmii util_gmii_to_rgmii_m0(
.reset(~rst_n),
//RGMII tx
.rgmii_td           (rgmii_txd      ),
.rgmii_tx_ctl       (rgmii_txctl    ),
.rgmii_txc          (rgmii_txc      ),
//RGMII rx
.rgmii_rd_i         (rgmii_rxd      ),
.rgmii_rx_ctl_i     (rgmii_rxctl    ),
.rgmii_rxc          (rgmii_rxc      ),//add

//GMII RX
.gmii_rx_clk        (gmii_rx_clk    ),
.gmii_rx_dv         (gmii_rx_dv     ),
.gmii_rx_er         (gmii_rx_er     ),
.gmii_rxd           (gmii_rxd       ),

//GMII TX
.gmii_txd           (e_txd        ),
.gmii_tx_en         (e_tx_en      ),
.gmii_tx_er         (1'b0           ),
.gmii_tx_clk        (gmii_tx_clk    ),

.gmii_crs           (gmii_crs       ),
.gmii_col           (gmii_col       ),

.speed_selection    (speed          ),
.duplex_mode        (duplex_mode    )

);

  BUFG bufmr_rgmii_rxc(
    .I(~rgmii_rxc),
    .O(gmii_rx_clk)
   );
修改为：
  BUFG bufmr_rgmii_rxc(
    .I(rgmii_rxc),
    .O(gmii_rx_clk)
   );