Yosys是一个开源综合工具,支持Verilog 2005。代码地址:https://github.com/YosysHQ/yosys
官网提到的功能如下:
Selected features and typical applications:
yum install bision
yum install flex
yum install readline
yum install readline-devel
yum install gwak
yum install graphviz
yum install pkgconfig
yum install boost
yum install boost-devel
yum install bzip2-devel
yum install tcl
yum install tcl-devel
yum install libffi
yum install libffi-devel
git clone https://github.com/YosysHQ/yosys
修改Makefile,编译并安装到指定目录。
#PREFIX ?= /usr/local
PREFIX = /home/cf/tools/yosys
make
make install
把/home/cf/tools/yosys/bin
加到环境变量PATH。
直接输入命令yosys
, 效果如下图, 键入help
可查看命令列表.
下面是官网的一个示例:
# read design
read_verilog mydesign.v
# elaborate design hierarchy
hierarchy -check -top mytop
# the high-level stuff
proc; opt; fsm; opt; memory; opt
# mapping to internal cell library
techmap; opt
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
# write synthesized design
write_verilog synth.v