在CentOS7上安装开源综合工具Yosys
介绍
Yosys是一个开源综合工具，支持Verilog 2005。代码地址：https://github.com/YosysHQ/yosys
官网提到的功能如下：
Selected features and typical applications:
- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows
安装依赖,包
yum install bision
yum install flex
yum install readline
yum install readline-devel
yum install gwak
yum install graphviz
yum install pkgconfig
yum install boost
yum install boost-devel
yum install bzip2-devel
yum install tcl
yum install tcl-devel
yum install libffi
yum install libffi-devel下载源码、编译、安装
下载
git clone https://github.com/YosysHQ/yosys编译、安装
修改Makefile，编译并安装到指定目录。
#PREFIX ?= /usr/local
PREFIX = /home/cf/tools/yosys
make
make install
配置
把/home/cf/tools/yosys/bin加到环境变量PATH。
使用
直接输入命令yosys, 效果如下图, 键入help可查看命令列表.
下面是官网的一个示例：
# read design
read_verilog mydesign.v
# elaborate design hierarchy
hierarchy -check -top mytop
# the high-level stuff
proc; opt; fsm; opt; memory; opt
# mapping to internal cell library
techmap; opt
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
# write synthesized design
write_verilog synth.v本文参与 腾讯云自媒体同步曝光计划，分享自微信公众号。
原始发表：2021-06-26，如有侵权请联系 cloudcommunity@tencent.com 删除
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