ReadMore:https://this-week-in-rust.org/blog/2022/02/02/this-week-in-rust-428/
rvv-encode RISC-V V 扩展指令库rvv-asm RISC-V V 扩展指令过程宏rvv-as RISC-V V 扩展指令的命令行工具rvv-asm例子unsafe {
rvv_asm::rvv_asm!(
"vsetvl x5, s3, t6",
"1: vle256.v v3, (a0), vm",
"2:",
"li {lo}, 4",
lo = out(reg) lo,
);
}rvv-as用法USAGE:
rvv-as [OPTIONS] <ASM_FILE>
ARGS:
<ASM_FILE> The original assembly source file path
OPTIONS:
-c, --comment-origin Use original instruction and its code as comment
-p, --comment-prefix <COMMENT_PREFIX> The comment prefix [default: #]
-r, --reserved-only Only translate reserved rvv instructionsReadMore:https://github.com/TheWaWaR/rvv-encoder
From 日报小组 冰山上的 mook && Mike