移位寄存器实现序列检测-Verilog「建议收藏」

//移位寄存器实现10010检测
module Detect_10010(
	input clk,
	input rst_n,
	input data_in,
	output reg [4:0] data_out,
	output flag
    );

always @ (posedge clk or negedge rst_n)
begin
	if(!rst_n)
		data_out <= 5'd0;
	else
		data_out <= ({ 
   data_out[3:0],data_in});
end

assign flag = (data_out == 5'b10010) ? 1'b1 : 1'b0;

endmodule