移位寄存器-Verilog

//五位循环右移
module register_right(
	input            clk,
	input 	   [4:0] data_in,
	output reg [4:0] data_out
    );
	 
    always @ (posedge clk)
    begin	
		data_out <= ({ 
   data_in[0],data_in[4:1]});
    end

endmodule