异步FIFO_Verilog实现「建议收藏」

module top(

		input	sys_clk,
		input	rst_n,

		input	[4:0]bin_code,
		output	[4:0]gray_code

    );
		
assign	gray_code = (bin_code>>1)^bin_code;

endmodule

module test_bench;

reg			sys_clk;
reg			rst_n;

reg		[4:0]bin_code;
wire	[4:0]gray_code;

top	u1
(
	.sys_clk	(sys_clk),
	.rst_n		(rst_n),
	.bin_code	(bin_code),
	.gray_code	(gray_code)
);

initial
begin
	rst_n 	= 0;	
	sys_clk = 0;
	bin_code= 5'b0_0000; #20; rst_n = 1; bin_code= 5'b1_0110;

end

always #10 sys_clk = ~sys_clk;

endmodule

module top
#
(
	parameter	FIFO_DEPTH = 8,
	parameter	FIFO_WIDTH = 16

)
(
		input						rst,
		
		input						wr_clk,
		input						wr_en,
		input	[FIFO_WIDTH-1:0]	din,
		output	reg					full,
			
		input						rd_clk,
		input						rd_en,
		output	[FIFO_WIDTH-1:0]	dout,
		output	reg					empty
);
	
//定义
reg		[FIFO_WIDTH-1:0]mem[FIFO_DEPTH-1:0];

reg		[3:0]	wr_add;
wire	[3:0]	wr_add_next;
wire	[3:0]	wr_add_gray_next;
reg		[3:0]	wp,wr1_rp,wr2_rp;

reg		[3:0]	rd_add;
wire	[3:0]	rd_add_next;
wire	[3:0]	rd_add_gray_next;
reg		[3:0]	rp,rd1_wp,rd2_wp;

wire			full_r;
wire			empty_r;

//输入数据
always@(posedge wr_clk)
begin
	if(wr_en && !full)
		mem[wr_add] <= din;
	else
		mem[wr_add] <= 16'h0000;
end

//输出数据
assign	dout = mem[rd_add];

//写时钟域
assign	wr_add_next 	 = wr_add + (wr_en & ~full);
assign	wr_add_gray_next = (wr_add_next>>1)^wr_add_next;
always@(posedge wr_clk or posedge rst)
begin
	if(rst)
		{ 
   wr_add,wp} <= { 
   4'b0000,4'b0000};
	else
		{ 
   wr_add,wp} <= { 
   wr_add_next,wr_add_gray_next};

end

//读时钟域
assign	rd_add_next 	 = rd_add + (rd_en & ~empty);
assign	rd_add_gray_next = (rd_add_next>>1)^rd_add_next;
always@(posedge rd_clk or posedge rst)
begin
	if(rst)
		{ 
   rd_add,rp} <= { 
   4'b0000,4'b0000};
	else
		{ 
   rd_add,rp} <= { 
   rd_add_next,rd_add_gray_next};
end

//读指针同步到写时钟域
always@(posedge wr_clk or posedge rst)
begin
	if(rst)
		{ 
   wr2_rp,wr1_rp} <= { 
   4'b0000,4'b0000};
	else
		{ 
   wr2_rp,wr1_rp} <= { 
   wr1_rp,rp};

end

//写时钟同步到读时钟域
always@(posedge rd_clk or posedge rst)
begin
	if(rst)
		{ 
   rd2_wp,rd1_wp} <= { 
   4'b0000,4'b0000};
	else
		{ 
   rd2_wp,rd1_wp} <= { 
   rd1_wp,wp};
end

//空信号判断
assign	empty_r = (rd2_wp == rd_add_gray_next)?1:0;
always@(posedge rd_clk or posedge rst)
begin
	if(rst)
		empty <= 1'b1;
	else
		empty <= empty_r;
end

//满信号判断
assign	full_r = (~wr2_rp[3:2] == wr_add_gray_next[3:2])?1:0;
always@(posedge wr_clk or posedge rst)
begin
	if(rst)
		full <= 1'b0;
	else
		full <= full_r;
end
	
endmodule

module test_bench;

reg						rst;
		
reg						wr_clk;
wire					wr_en;
reg	[15:0]				din;
wire					full;
	
reg						rd_clk;
wire					rd_en;
wire [15:0]				dout;
wire					empty;

wire[15:0]				data_out;

top	u1
(
	.rst	(rst),
	
	.wr_clk	(wr_clk),
	.wr_en	(wr_en),
	.din	(din),
	.full	(full),
	
	.rd_clk	(rd_clk),
	.rd_en  (rd_en ),
	.dout   (dout  ),
	.empty  (empty )
);

initial
begin
	rst 	= 1;	
	wr_clk	= 0;
	rd_clk	= 0;


	#50;
	rst 	= 0;	

end
//FIFO Write
assign	wr_en 		=(rst==1)?1'b0: !full;

always@(posedge wr_clk or posedge rst)
begin
	if(rst)
	begin
		din			<= 16'h0000;
	end
	else if(wr_en == 1'b1)
	begin
		din 		<= (din == 16'd8)?16'h0000:din + 16'd1;
	end
	else
	begin	
		din			<= 16'h0000;
	end
end
//FIFO Read
assign	rd_en 	 = !empty;

assign	data_out = (rd_en==1'b1)?dout:16'h0000;


//时钟产生
always #10 wr_clk = ~wr_clk;
always #15 rd_clk = ~rd_clk;

endmodule