FPGA：Verilog HDL程序的基本结构

/* Gate-level description of a half adder */
module HalfAdder_GL(A, B, Sum, Carry);
  input  A ,B ;		//输入端口声明
  output  Sum, Carry ;      //输出端口声明
  wire A ,B , Sum ,Carry ; 
  
  xor X1 (Sum, A, B );
  and A1 (Carry, A, B);  
endmodule

/* Dataflow description of a half adder */
module HalfAdder_DF(A, B, Sum, Carry);
  input  A ,B ;	 	 
  output  Sum ,Carry ; 
  wire A ,B，Sum ,Carry ; 
  assign   Sum = A ^ B; 
  assign   Carry = A & B; 
endmodule

/* Behavioral description of a half adder */
module HalfAdder_BH(A, B, Sum, Carry);
  input  A ,B ;	 	  
  output  Sum ,Carry ; 
  reg Sum ,Carry ;        //声明端口数据类型为寄存器
  always @(A or B)  begin
	Sum = A ^ B;	      //用过程赋值语句描述逻辑功能
	Carry = A & B;
  end
endmodule

module mux2to1(a, b, sel, out);
  input a, b, sel;   //定义输入信号
  output out;        //定义输出信号
  wire selnot,a1,b1; //定义内部节点信号数据类型
 //下面对电路的逻辑功能进行描述
  not U1(selnot, sel);
  and U2(a1, a, selnot);
  and U3(b1, b, sel);
  or  U4(out, a1, b1); 
endmodule

module mux2_1(out, a, b, sel) ;
    output   out;
    input  a, b;
    input sel;
     reg out;

    always @(sel or a or b)
       begin
          if (sel) 
                      out = b;
          else     out = a;
       end
endmodule

module mux2_1(out, a, b, sel) ;
    output   out;
    input  a, b;
    input sel;
    reg out;
    always @(sel or a or b)
       begin
          case (sel)
              1’b0 :  out = a;
              1’b1 :  out = b;
          endcase
       end
endmodule

module模块名(端口名1，端口名2，端口名3,…) ;
	端口类型说明(input, output, inout);
	参数定义(可选);
	数据类型定义(wire, reg等);

	实例化低层模块和基本门级元件;
	连续赋值语句(assign);
	过程块结构(initial和always)
		行为描述语句;
endmodule