AMD Xilinx AXI Interrupt Controller 中断优先级

Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority.

Intr(0) is always the highest priority interrupt and each successive bit to the left has a corresponding lower interrupt priority.

Nested Interrupts
The core provides support for nested interrupts, by implementing an Interrupt Level 
Register. This can be used by software to prevent lower priority interrupts from occurring 
when handling an interrupt, thus allowing interrupts to be enabled during interrupt 
handling to immediately take a higher priority interrupt. Software must save and restore 
the Interrupt Level Register and return address.
Because the processor jumps directly to the unique Interrupt vector address to service a 
particular interrupt when using fast interrupt mode, the user interrupt service routine code itself must save and restore the Interrupt Level Register and Return Address in this case. In 
normal interrupt mode, this is handled by the software driver.

For nested interrupts, XIntc_DeviceInterruptHandler saves
microblaze r14 register on entry and restores on exit. This is
required since compiler does not support nesting. It enables
Microblaze interrupts after blocking further interrupts from
the current interrupt number and interrupts below current
interrupt priority by writing to Interrupt Level Register of
INTC on entry. On exit, it disables microblaze interrupts and
restores ILR register default value(0xFFFFFFFF)back. It is
recommended to increase STACK_SIZE in linker script for nested
interrupts.