modelsim说：")"：(vcom-1576)期望标识符。但是修复它会带来更多的错误。
modelsim说：")"：(vcom-1576)期望标识符。但是修复它会带来更多的错误。
提问于 2022-06-24 16:00:08
使用此代码时：
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_STD.all;
entity CLOCKDIVIDER_TB is
end entity CLOCKDIVIDER_TB;
architecture BENCH of CLOCKDIVIDER_TB is
--declare component
component ClockDivider
Port(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK_OUT_DIV_01 : OUT STD_LOGIC;
CLK_OUT_DIV_02 : OUT STD_LOGIC;
CLK_OUT_DIV_03 : OUT STD_LOGIC;
CLK_OUT_DIV_04 : OUT STD_LOGIC;
);
end component;
--inputs
signal CLK : IN STD_LOGIC := '0';
signal RST : IN STD_LOGIC := '0';
--outputs
signal CLK_OUT_DIV_01 : OUT STD_LOGIC;
signal CLK_OUT_DIV_02 : OUT STD_LOGIC;
signal CLK_OUT_DIV_03 : OUT STD_LOGIC;
signal CLK_OUT_DIV_04 : OUT STD_LOGIC;
--clock period
constant clk_t : time := 20 ns;
BEGIN
--uut instance
uut: ClockDivider PORT MAP (
CLK => CLK,
RST => RST,
CLK_OUT_DIV_01 => CLK_OUT_DIV_01,
CLK_OUT_DIV_02 => CLK_OUT_DIV_02,
CLK_OUT_DIV_03 => CLK_OUT_DIV_03,
CLK_OUT_DIV_04 => CLK_OUT_DIV_04
);
-- Clock definition.
clk_process: process
begin
CLK <= '0';
wait for clk_t / 2;
CLK <= '1';
wait for clk_t / 2;
end process;
-- Processing.
stim_proc: process
begin
wait for 100 ns;
reset <= '1'; -- Up
wait for 100 ns;
reset <= '0'; -- Down
wait;
end process;
end architecture BENCH;我发现了一个错误：
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(27): near ")": (vcom-1576) expecting IDENTIFIER.但是，当通过删除组件声明中的分号来修复此错误时：
--declare component
component ClockDivider
Port(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK_OUT_DIV_01 : OUT STD_LOGIC;
CLK_OUT_DIV_02 : OUT STD_LOGIC;
CLK_OUT_DIV_03 : OUT STD_LOGIC;
CLK_OUT_DIV_04 : OUT STD_LOGIC
);程序给出了以下错误：
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(31): near "IN": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(32): near "IN": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(35): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(36): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(37): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(38): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(47): (vcom-1136) Unknown identifier "CLK".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(48): (vcom-1136) Unknown identifier "RST".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(49): (vcom-1136) Unknown identifier "CLK_OUT_DIV_01".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(50): (vcom-1136) Unknown identifier "CLK_OUT_DIV_02".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(51): (vcom-1136) Unknown identifier "CLK_OUT_DIV_03".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(52): (vcom-1136) Unknown identifier "CLK_OUT_DIV_04".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(58): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(58): (vcom-1136) Unknown identifier "CLK".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(60): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(60): (vcom-1136) Unknown identifier "CLK".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(68): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(68): (vcom-1136) Unknown identifier "reset".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(70): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(70): (vcom-1136) Unknown identifier "reset". 当我修复语法错误时，我不太清楚为什么程序会中断。
我对这个程序也很陌生，我不能用其他的例子来找出问题所在。
有人知道怎么解决这个问题吗？
回答 1
Stack Overflow用户
发布于 2022-06-25 08:55:08
谢谢你的帮助。我仔细检查了代码，并设法让它正常工作。我意识到我的错误，我混淆了复位和RST，以及删除“输入”和“输出”在声明信号。
这是工作代码：
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_STD.all;
entity CLOCKDIVIDER_TB is
end entity CLOCKDIVIDER_TB;
architecture BENCH of CLOCKDIVIDER_TB is
--declare component
component ClockDivider
Port(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK_OUT_DIV_01 : OUT STD_LOGIC;
CLK_OUT_DIV_02 : OUT STD_LOGIC;
CLK_OUT_DIV_03 : OUT STD_LOGIC;
CLK_OUT_DIV_04 : OUT STD_LOGIC
);
end component;
--signals
--inputs
signal CLK : STD_LOGIC := '0';
signal RST : STD_LOGIC := '0';
--outputs
signal CLK_OUT_DIV_01 : STD_LOGIC;
signal CLK_OUT_DIV_02 : STD_LOGIC;
signal CLK_OUT_DIV_03 : STD_LOGIC;
signal CLK_OUT_DIV_04 : STD_LOGIC;
--clock period
constant clk_t : time := 20 ns;
BEGIN
--uut instance
uut: ClockDivider PORT MAP (
CLK => CLK,
RST => RST,
CLK_OUT_DIV_01 => CLK_OUT_DIV_01,
CLK_OUT_DIV_02 => CLK_OUT_DIV_02,
CLK_OUT_DIV_03 => CLK_OUT_DIV_03,
CLK_OUT_DIV_04 => CLK_OUT_DIV_04
);
-- Clock definition.
clk_process: process
begin
CLK <= '0';
wait for clk_t / 2;
CLK <= '1';
wait for clk_t / 2;
end process;
-- Processing.
stim_proc: process
begin
RST <= '1';
wait for 1 ns;
RST <= '0';
wait for 2000000 ns;
RST <= '1'; -- Up
wait;
end process;
end architecture BENCH;页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/72746637
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