问VHDL中的If-语句:嵌套和多个条件

EN

signal  lowBound        :   std_logic_vector(15 downto 0);
signal  highBound       :   std_logic_vector(15 downto 0);
signal  result_01       :   std_logic_vector(15 downto 0);
signal  result_02       :   std_logic_vector(15 downto 0);
signal  result_03       :   std_logic_vector(15 downto 0);

...
p_state_machine: process(RESET, CLK)
    if (RESET = '1') then
        ...
    elsif (rising_edge(CLK_I)) then
        case currentState is
            when ...
            ...
            when OUTPUT =>
                -- check if results are within interval bounds
                -- option 1
                if ((result_01 > lowBound) AND (result_02 > lowBound) AND (result_03 > lowBound) AND ...) then
                    ...
                end if;

                -- option 2
                if ((result_01 > lowBound) then
                    if ((result_02 > lowBound) then
                        if ((result_03 > lowBound) then
                            ...
                        end if;
                    end if;
                end if;
        end case;
    end if;
end process;