基于6U VPX 4片DSP6678+FPGA KU115高性能处理板-设计原理参考设计+调试接口技术指南

板卡基于标准6U VPX架构，板载一片Xilinx FPGA XCKU115-2FLVF1924I和四片 TI 多核DSP TMS320C6678，每个DSP有配有2GB的储存空间，该板卡可以通过PCIE、SRIO和SGMII接口与背板进行高速数据传输。板内还有一个MCU：IPMB模块，既可以管理系统复位，又可以监控板内温度、电压和电流。

板卡特性

l DSP x4：

Ø DSP：四片TMS320C6678ACYPA

Ø DDR3：64bit，2GB，1333MT/s

Ø UART：1路

Ø 千兆以太网：1路

Ø 加载方式：GPIO，EMIF

l FPGA：

Ø Xilinx：XCKU115-2FLVF1924

Ø DDR4：1组32bit，2GB，2400MT/s

Ø 加载方式：BPI NorFlash

l 互联：

Ø DSP1和DSP2间：Hyperlink x4

Ø DSP3和DSP4间：Hyperlink x4

Ø DSP1和KU115间：EMIF x16,GPIO x16

Ø DSP2和KU115间：EMIF x16,GPIO x16，SRIOx4

Ø DSP3和KU115间：EMIF x16,GPIO x16

Ø DSP4和KU115间：EMIF x16,GPIO x16，SRIOx4

l 接口：

Ø VPXP0：IPMB

Ø VPXP1：4组SRIO x4

Ø VPXP2：2组SRIO x4，3组SYNC

Ø VPXP3：16组SFP x1

Ø VPXP4：4组SGMII，LED x32

Ø J30J：FPGA、DSP1-4 JTAG、DSP UART、IPMB USB,JTAG

l 物理与电气特性

Ø 板卡尺寸：160mmX233.35mm

Ø 板卡供电：+12V@10A

Ø 散热方式：风冷

l 环境特征

Ø 工作温度：-40℃~+85℃

Ø 存储温度：-55℃~+125℃

工作湿度：45%~70% RH

接口介绍

测试报告

DDR读写：

FLASH烧写

DSP程序加载

UART测试：

DSP SRIO-VPX Link测试

DSP SGMII-VPX Link测试：

DSP Hyperlink测试

Hyperlink test starts:

Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:17:16

About to do system setup (PLL, PSC, and DDR)

Constructed SERDES configs: PLL=0x00000030; RX=0x0046c485; TX=0x000cc305

system setup worked

About to set up HyperLink Peripheral

============== begin registers before initialization ===========

Revision register contents:

Raw    = 0x4e901900

Status register contents:

Raw        = 0x00002004

Link status register contents:

Raw       = 0x00000000

Control register contents:

Raw             = 0x00000001

Control register contents:

Raw        = 0x00000000

============== end registers before initialization ===========

SERDES_STS (32 bits) contents: 0x03068919; lock = 1

============== begin registers after initialization ===========

Status register contents:

Raw        = 0x04400005

Link status register contents:

Raw       = 0xccf00cf0

Control register contents:

Raw             = 0x00006200

============== end registers after initialization ===========

Waiting 5 seconds to check link stability

Precursors 0 Analysis: 0,1,1,0,1,0,0,0

Postcursors: 19 Analysis: 1,0,1,0,0,1,1,0

Link seems stable

About to try to read remote registers

============== begin REMOTE registers after initialization ===========

Status register contents:

Raw        = 0x0440000b

Link status register contents:

Raw       = 0xfdf0bdf0

Control register contents:

Raw             = 0x00006200

============== end REMOTE registers after initialization ===========

Peripheral setup worked

About to read/write once

Single write test passed

Trans rate :148.750873 MByte/s .

Link Speed is 4 * 7.5 Gbps

Test Completed successfully