问fpga无法获得简单的寄存器输出
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Stack Overflow用户

提问于 2018-06-30 11:03:31

回答 1查看 108关注 0票数 1

我知道这是基本的，但我很难让它工作。我正在从IO引脚中“读取”，并且我想将这些位“保存”在一个简单的缓冲区中。由于某种原因，我在输出中没有得到任何东西。这是我正在运行的代码和bench的网表分析器，以及我通过运行测试平台得到的波形。我尝试应用我在其他代码中看到的东西，但它不起作用。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity InputBuffer is
    generic( n: natural := 4 );
    Port (    
        clk    : in STD_LOGIC;
        CLK65  : IN STD_LOGIC;
        En     : in STD_LOGIC;
        STRT   : OUT STD_LOGIC;
        Ipin   : in  STD_LOGIC_VECTOR (n-1 downto 0);
        Output : out  STD_LOGIC_VECTOR (n-1 downto 0)
        );
end InputBuffer;

architecture Behavioral of InputBuffer is
    signal temp : STD_LOGIC_VECTOR(n-1 downto 0);
    SIGNAL CLK2 : STD_LOGIC;
begin
    -- invert the signal from the push button switch and route it to the LED
    process(clk, En)
    begin
        if( En = '1') then
            temp <= B"0000";
        elsif rising_edge(clk) then
            temp <= Ipin; 
        end if;
    end process;
    Output <=  temp;
    STRT <= CLK65;
end Behavioral;

这是我正在使用的测试平台。

     -- VHDL Test Bench Created from source file InputBuffer.vhd -- Fri Jun 29 22:45:57 2018

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

    COMPONENT InputBuffer
    PORT(
        clk : IN std_logic;
        CLK65 : IN std_logic;
        En : IN std_logic;
        Ipin : IN std_logic_vector(3 downto 0);          
        STRT : OUT std_logic;
        Output : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;

    SIGNAL clk :  std_logic;
    SIGNAL CLK65 :  std_logic;
    SIGNAL En :  std_logic;
    SIGNAL STRT :  std_logic;
    SIGNAL Ipin :  std_logic_vector(3 downto 0);
    SIGNAL Output :  std_logic_vector(3 downto 0);  

    constant delay : time := 10 ns;

BEGIN

-- Please check and add your generic clause manually
    uut: InputBuffer PORT MAP(
        clk => clk,
        CLK65 => CLK65,
        En => En,
        STRT => STRT,
        Ipin => Ipin,
        Output => Output
    );

    En <= '0';
    clk <= '0';
    clk65 <= '0';
    Ipin <= B"0000";
-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN  
      wait for delay;
      clk <='1'; 
      clk65 <='1';
      wait for delay;
      clk <='0';


      wait for delay;
      clk <='1';
      clk65 <='0';

      wait for delay;
      clk <='0';
      --wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;