iverilog错误可能源于不正确的变量类型?

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我是verilog编程的新手,正在使用2个4位比较器实现8位无符号幅度比较器。我相信我的代码是正确实现的,但我收到的错误,我认为是由于不正确的变量类型分配。由于我是这门语言的新手,我认为这是一个学习机会,但是我找不到足够的相关材料来引导我找到解决方案。如果有人可以解释为什么我使用的类型不正确(或者如果它是我面临的另一个问题),那将非常感激。

编辑:我改变了建议的答案,模块实例化在always块之外,导线为eq,gt和lt,但仍然出现错误。更新了错误代码。

module MagComp4Bit (input [3:0] a, input [3:0] b, output eq, output gt, output lt);

    assign eq = a==b;
    assign gt = a>b;
    assign lt = a<b;

endmodule

module MagComp8Bit (input [7:0] a, input [7:0] b, output eq, output gt, output lt);

    reg eq0, gt0, lt0, eq1, gt1, lt1;

    MagComp4Bit comp1(a[3:0], b[3:0], eq0, gt0, lt0);
    MagComp4Bit comp2(a[7:4], b[7:4], eq1, gt1, lt1);
    always @(a, b)
    begin


            if (eq1) begin
                    eq = eq0? 1 : 0;
                    gt = gt0? 1 : 0;
                    lt = lt0? 1 : 0;
            end
            else begin
                    gt = gt1? 1 : 0;
                    lt = lt1? 1 : 0;
            end
    end
endmodule

module TestComparator;
    reg[7:0] a, b;
    wire eq, gt, lt;

    MagComp8Bit compare(a, b, eq, gt, lt);

    initial begin
            $moniter("%d a=%b, b=%b, eq=%b, gt=%b, lt=%b",
                    $time, a, b, eq, gt, lt);

            #10     a = 2;
                    b = 5;
    end
endmodule

错误信息:

hw1p1.v:13: error: reg eq0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 3 (eq) of MagComp4Bit is connected to eq0
hw1p1.v:13: error: reg gt0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 4 (gt) of MagComp4Bit is connected to gt0
hw1p1.v:13: error: reg lt0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 5 (lt) of MagComp4Bit is connected to lt0
hw1p1.v:14: error: reg eq1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 3 (eq) of MagComp4Bit is connected to eq1
hw1p1.v:14: error: reg gt1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 4 (gt) of MagComp4Bit is connected to gt1
hw1p1.v:14: error: reg lt1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 5 (lt) of MagComp4Bit is connected to lt1
hw1p1.v:22: error: eq is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : eq is declared here as wire.
hw1p1.v:23: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : gt is declared here as wire.
hw1p1.v:24: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : lt is declared here as wire.
hw1p1.v:27: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : gt is declared here as wire.
hw1p1.v:28: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : lt is declared here as wire.
17 error(s) during elaboration.

(PS我知道将测试台包含在其他模块中是不合适的,但是当我能够立刻看到它时,我更容易学习。)

提问于
用户回答回答于

wire类型不能在任何程序块中分配(总是,初始,...)。你正在做的内部always

always...  
    .. 
    eq = eq0? 1 : 0;

where eq被定义为没有任何数据类型的端口,这意味着wire默认情况下。其他2个端口相同:ltgt

您需要稍微更改一下代码:

reg eqReg, ltReg, wrReg;

always @(a, b)
    begin

        if (eq1) begin
                eqReg = eq0? 1 : 0;
                gtReg = gt0? 1 : 0;
                ltReg = lt0? 1 : 0;
        end
        else begin
                gtReg = gt1? 1 : 0;
                ltReg = lt1? 1 : 0;
        end
end
assign eq = eqReg;
assign lt = ltReg;
assign gt = gtReg;
用户回答回答于

Verilog模块不能在initial或always块中实例化。这就是你应该移动的原因:

MagComp4Bit(a[3:0], b[3:0], eq0, gt0, lt0);
MagComp4Bit(a[7:4], b[7:4], eq1, gt1, lt1);

外面的always街区。更重要的是,eq, gt, lt应该在TestComparator模块中声明为连线。

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