iverilog错误可能源于不正确的变量类型
iverilog错误可能源于不正确的变量类型
提问于 2018-09-26 09:35:51
我刚接触verilog编程，正在使用2个4位比较器实现一个8位无符号幅度比较器。我相信我的代码是正确实现的，但是我收到了错误，我认为这些错误是由于变量类型分配不正确造成的。由于我刚接触这门语言，我认为这是一个学习的机会，但是我找不到足够的相关材料来引导我找到解决方案。如果有人能解释为什么我使用的类型是不正确的(或者如果这是我面临的另一个问题)，我将不胜感激。
编辑:我将我的答案改为建议的，在always块和连接之外的模块实例化为eq，gt和lt，但仍然收到错误。已更新错误代码。
module MagComp4Bit (input [3:0] a, input [3:0] b, output eq, output gt, output lt);
assign eq = a==b;
assign gt = a>b;
assign lt = a<b;
endmodule
module MagComp8Bit (input [7:0] a, input [7:0] b, output eq, output gt, output lt);
reg eq0, gt0, lt0, eq1, gt1, lt1;
MagComp4Bit comp1(a[3:0], b[3:0], eq0, gt0, lt0);
MagComp4Bit comp2(a[7:4], b[7:4], eq1, gt1, lt1);
always @(a, b)
begin
if (eq1) begin
eq = eq0? 1 : 0;
gt = gt0? 1 : 0;
lt = lt0? 1 : 0;
end
else begin
gt = gt1? 1 : 0;
lt = lt1? 1 : 0;
end
end
endmodule
module TestComparator;
reg[7:0] a, b;
wire eq, gt, lt;
MagComp8Bit compare(a, b, eq, gt, lt);
initial begin
$moniter("%d a=%b, b=%b, eq=%b, gt=%b, lt=%b",
$time, a, b, eq, gt, lt);
#10 a = 2;
b = 5;
end
endmodule错误消息：
hw1p1.v:13: error: reg eq0; cannot be driven by primitives or continuous
assignment.
hw1p1.v:13: error: Output port expression must support continuous
assignment.
hw1p1.v:13: : Port 3 (eq) of MagComp4Bit is connected to eq0
hw1p1.v:13: error: reg gt0; cannot be driven by primitives or continuous
assignment.
hw1p1.v:13: error: Output port expression must support continuous
assignment.
hw1p1.v:13: : Port 4 (gt) of MagComp4Bit is connected to gt0
hw1p1.v:13: error: reg lt0; cannot be driven by primitives or continuous
assignment.
hw1p1.v:13: error: Output port expression must support continuous
assignment.
hw1p1.v:13: : Port 5 (lt) of MagComp4Bit is connected to lt0
hw1p1.v:14: error: reg eq1; cannot be driven by primitives or continuous
assignment.
hw1p1.v:14: error: Output port expression must support continuous
assignment.
hw1p1.v:14: : Port 3 (eq) of MagComp4Bit is connected to eq1
hw1p1.v:14: error: reg gt1; cannot be driven by primitives or continuous
assignment.
hw1p1.v:14: error: Output port expression must support continuous
assignment.
hw1p1.v:14: : Port 4 (gt) of MagComp4Bit is connected to gt1
hw1p1.v:14: error: reg lt1; cannot be driven by primitives or continuous
assignment.
hw1p1.v:14: error: Output port expression must support continuous
assignment.
hw1p1.v:14: : Port 5 (lt) of MagComp4Bit is connected to lt1
hw1p1.v:22: error: eq is not a valid l-value in TestComparator.compare.
hw1p1.v:9: : eq is declared here as wire.
hw1p1.v:23: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9: : gt is declared here as wire.
hw1p1.v:24: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9: : lt is declared here as wire.
hw1p1.v:27: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9: : gt is declared here as wire.
hw1p1.v:28: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9: : lt is declared here as wire.
17 error(s) during elaboration.(附注:我知道将测试台与其他模块一起包含是不合适的，但当我可以一次看到所有模块时，对我来说更容易学习。)
回答 2
Stack Overflow用户
回答已采纳
发布于 2018-09-26 13:45:18
Verilog模块不打算在initial或always块中实例化。这就是你应该搬家的原因：
MagComp4Bit(a[3:0], b[3:0], eq0, gt0, lt0);
MagComp4Bit(a[7:4], b[7:4], eq1, gt1, lt1);在always块之外。此外，应该在TestComparator模块中将eq, gt, lt声明为wires。
Stack Overflow用户
发布于 2018-09-27 07:03:18
不能在任何程序块中指定wire类型(始终、初始、..)。您在always中执行的是jus
always...
..
eq = eq0? 1 : 0;其中，eq定义为没有任何数据类型的端口，默认情况下表示wire。其他2个端口也是如此：lt和gt。
你需要稍微修改一下你的代码：
reg eqReg, ltReg, wrReg;
always @(a, b)
begin
if (eq1) begin
eqReg = eq0? 1 : 0;
gtReg = gt0? 1 : 0;
ltReg = lt0? 1 : 0;
end
else begin
gtReg = gt1? 1 : 0;
ltReg = lt1? 1 : 0;
end
end
assign eq = eqReg;
assign lt = ltReg;
assign gt = gtReg;页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/52508744
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