问VHDL有限状态机多驱动网络Q连接到常量驱动，其他驱动被忽略，我的代码有什么问题？

EN

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity simpfsm is
Port ( A : in STD_LOGIC;
       clk : in STD_LOGIC;
       r   : in STD_LOGIC;
       Y : out STD_LOGIC);
end simpfsm;


architecture Behavioral of simpfsm is
type state_type is (SA,SB,SC);
signal state,next_state:state_type;
begin
SYNC_PROC:process(clk)
begin
if(clk'event and clk='1') then
if(r='1') then
next_state <= SA; -- removed trailing grave accent
else
state <= next_state;
end if;
end if;
end process;

OUTPUT_DECODE:process(state)
begin
case (state) is
when SA =>
Y <= '0';
when SB =>
Y <= '0';
when SC =>
Y <= '1';
when others =>
Y <= '0';
end case;
end process;

NEXT_STATE_DECODE:process(state,A)
begin
next_state <= state;
case (state) is

    when SA =>
        if(A='0') then
            next_state <= SB;
        end if;

    when SB =>
        if(A='1') then
            next_state <= SC;
        end if;

    when SC =>
        if(A='0') then
            next_state <= SB;
        elsif(A='1') then
            next_state <= SA;
        end if;
    when others =>
        next_state <= SA;                       --"if not state then begin with SA"
end case;
end process;
end Behavioral;  -- removed trailing grave accent