blocks|key|4338755|text|硬件中断由物理信号产生，或者来自微控制器本身(例如，作为总线控制器的一部分)，或者来自配置为中断的外部GPIO。这些中断通常与与微控制器外部的硬件的交互有关，例如当总线上发生事件时产生的SPI或I2C总线中断。这些硬件中断通常通过控制寄存器和中断屏蔽的组合来配置，控制寄存器指定硬件行为，中断屏蔽允许在任何时间点启用或禁用某些中断。电源事件、定时器等内部硬件事件也会触发中断。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|4338756|软件中断由微控制器执行的指令产生。例如，在x86平台上，您可以使用INT3指令引发陷阱中断以进行调试。软件中断通常用作切换特权级别的方式，例如利用系统调用，因为在低特权模式下运行的代码可以触发在高特权模式下执行的中断，然后该中断可以适当地分派系统调用请求。|offset|length|style|CODE|4338757|在这两种情况下，通常使用中断向量表配置中断处理程序。中断向量仅仅是指向处理每个中断的函数的指针。该表通常存在于微控制器的闪存或ROM空间中的固定内存位置，但在许多情况下，中断表位置可以配置为编程过程的一部分。通常，每种中断类型都有一个与其在中断表中的索引相对应的数字，因此您知道将每个处理程序的向量放在哪里。|4338758|entityMap^0|0|X|4|0|0^^$0|@$1|2|3|4|5|6|7|L|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|M|8|@$D|N|E|O|F|G]]|9|@]|A|$]]|$1|H|3|I|5|6|7|P|8|@]|9|@]|A|$]]|$1|J|3|-4|5|6|7|Q|8|@]|9|@]|A|$]]]|K|$]]

Hardware interrupts are generated by physical signals, either from within the microcontroller itself (e.g. as part of a bus controller) or from an external GPIO configured as an interrupt. These interrupts are usually related to interactions with hardware external to the microcontroller, e.g. SPI or I2C bus interrupts generated when an event occurs on the bus. These hardware interrupts are usually configured via a combination of control registers, which specify hardware behaviour, and interrupt masking, which allows certain interrupts to be enabled or disabled at any point in time. Internal hardware events such as power events, timers, etc. also trigger interrupts.

Software interrupts are generated by instructions executed by the microcontroller. For example, on x86 platforms you can use an <code>INT3</code> instruction to raise a TRAP interrupt for debugging purposes. Software interrupts are commonly used as a way to switch privilege levels, e.g. with syscalls, since code running in a low-privilege mode can trigger an interrupt which executes in a high-privilege mode, which can then dispatch the syscall request appropriately.

In both cases, interrupt handlers are generally configured using an interrupt vector table. Interrupt vectors are simply pointers to functions that handle each interrupt. The table usually exists at a fixed memory location in the microcontroller's flash or ROM space, but in many situations the interrupt table location can be configured as part of the programming process. Generally, each interrupt type is given a number which corresponds to its index in the interrupt table, so you know where to put each individual handler's vector.

blocks|key|4338829|text|它们都是中断，它只与源有关。有些中断(这些也是信号)是由指令或故障等(未定义、未对齐等)生成的。以及一些对芯片供应商可用的。ARM制造IP而不是芯片，芯片供应商被提供了许多中断，他们可以选择使用他们想要的任何方式。它们通常与usb、gpio、uart、spi等外围设备绑定。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|4338830|ARM有一个称为swi软件中断或svc的中断。就像x86中的软中断数量一样，例如，这是为了让应用程序可以进行服务调用。在全尺寸arm上，这可以在较低/最高执行级别执行，但由更高、更有特权的模式或执行级别提供服务。基本上允许你拥有一个操作系统。可以在cortex-m上使用此功能，但没有保护层，它提供了一个通用接口，例如，当您下载了rtos并想为其编写应用程序时，rtos是通用的，应用程序可以做您想要或需要完成的事情，并且可以使用此接口调用rtos+(由rtos定义)。无论是arm还是x86，调用都是任意的，逻辑并不规定，软件规定，传统的x86有用于特定中断的bios处理程序，但这是任意的，你可以编写自己的bios/处理程序，这与传统不兼容，只要双方在接口上达成一致，它就会工作得很好，同样，arm的swi/svc调用不一定是标准的，linux可能有一个，但如果他们不想这样做，自由实时操作系统就不需要遵守这一点。|4338831|皮质-M的情况下的另一个不同之处在于，所谓的外部中断具有或可以具有额外的屏蔽层，使得您可以使用中断控制器来禁用它们，其中事件类型中断如未定义的、系统棒等，尽管只是信号不通过屏蔽层，但是在内核外部但通常与芯片供应商提供的项目相关的所谓外部中断是通用的或必要的。并不是所有供应商(arm、英特尔、mips等)的所有架构都适用，但如果我没记错的话，cortex+m就是这样实现的。诚然，不断有新的内核出现，他们没有任何理由以相同的方式设计所有这些内核。|4338832|entityMap^0|0|0|0^^$0|@$1|2|3|4|5|6|7|H|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|I|8|@]|9|@]|A|$]]|$1|D|3|E|5|6|7|J|8|@]|9|@]|A|$]]|$1|F|3|-4|5|6|7|K|8|@]|9|@]|A|$]]]|G|$]]

they are all interrupts it just has to do with the source. there are some interrupts (these are signals too) that are generated by instructions or faults, etc (undefined, unaligned, etc). And some that are available to the chip vendor. ARM makes IP not chips, the chip vendor is provided with a number of interrupts they can choose to use however they wish. Often they are tied to peripherals like usb, gpio, uart, spi, etc.

ARM has one called swi software interrupt or svc. And like the number of soft interrupts in x86, this is for example so that an application can make a service call. On a full sized arm this can be executed at the lower/est execution levels but is serviced by a higher more privileged mode or execution level. basically allowing you to have an operating system. Can use this feature on the cortex-m but doesnt have the protection layers it provides a common interface for example when you have downloaded an rtos and want to write applications for it, the rtos is generic-ish and the applications are yours doing what you want or need to get done and can make calls into the rtos (defined by the rtos) using this interface. be it arm or x86 the calls are really arbitrary, logic doesnt dictate, the software dictates, traditionally x86 has bios handlers for specific interrupts, but that is arbitrary, you can write your own bios/handler that is incompatible with tradition and it will work just fine so long as both sides agree on the interface, likewise swi/svc calls for arm are not necessarily a standard, linux might have one but freertos doesnt have to conform to that if they dont want to.

another difference in the case of the cortex-m but is not necessarily a universal differences nor required, is that the so called external interrupts which are external to the core but generally tied to items provided by the chip vendor, have or may have an extra layer of masking, so that you can disable them using an interrupt controller, where the event type interrupts like undefined, systick, etc although are just signals do not go through a masked layer. not universally true for all architectures from all vendors (arm, intel, mips, etc), but if I remember right in the case of the cortex-m this is how they implemented it. granted there continue to be new cores coming out and there is no reason whatsoever for them to design all of them the same way.

blocks|key|4338500|text|硬件中断由soundchip等硬件触发，而软件中断由软件触发，因为它是程序指令|type|unstyled|depth|inlineStyleRanges|entityRanges|data|4338501|entityMap^0|0^^$0|@$1|2|3|4|5|6|7|D|8|@]|9|@]|A|$]]|$1|B|3|-4|5|6|7|E|8|@]|9|@]|A|$]]]|C|$]]

Hardware interrupt is triggered by hardware like soundchip while software interrupt is triggered by software since it is a program instruction

I have recently started working on ARM Cortex Microcontrollers. While reading different articles over Internet, I usually found 2 common terms as Software Interrupt and Hardware Interrupt.
What is the actual difference in both? Can you explain with an example?

Difference between Software and Hardware Interrupts

微控制器

我最近开始研究ARM Cortex微控制器。在互联网上阅读不同的文章时，我通常会发现两个常见的术语:软件中断和硬件中断。这两者的实际区别是什么？你能举个例子解释一下吗？

问软件中断和硬件中断之间的区别
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