问如何将奇偶校验位附加到给定的4位std_logic_vector？

EN

architecture rtl of odd parity is
    signal rxdat_s   : out std_logic_vector(3 downto 0);
    signal ok_s      : out std_logic;
    signal txdat_s   : in std_logic_vector(3 downto 0);
    signal secured_s : std_logic_vector (4 downto 0);

begin 
    odd_parity_gen: process ( txdat_s, clk ) is
        variable txdat_v      : std_logic_vector(3 downto 0);
        variable secured_v    : std_logic_vector(4 downto 0);
        variable odd_parity_v : integer;
    begin 
        txdat_v := txdat_s;

        odd_parity_v := xnor txdat_v;
        secured_v    := txdat_v + odd_parity_v;

        secured_s <= secured_v;

    end process odd_parity_gen;

    odd_parity_check: process () is
        variable ok_v         : integer;
        variable rxdat_v      : std_logic_vector(3 downto 0);
        variable secured_v    : std_logic_vector(4 downto 0);
    begin
        rxdat_v   := rxdat_s;
        secured_v := secured_s;
        ok_v      := ok_s;

        ok_v    := xnor secured_v;
        rxdat_v := secured_v;

        ok_s    <= ok_v;
        rxdat_s <= rxdat_v;


    reg: process ( clk ) is
    begin
        if rising_edge (clk) then 
            if nres = '0' then
                --reset all signals
            else
                --main logic
            end if;
        end if;
    end process;