创建UCF文件时出现错误？
创建UCF文件时出现错误？
提问于 2013-06-10 20:59:49
在使用以太网在spartan 6上创建一个简单的microblaze之后，使用EDK创建Microbalze会在同一目录的data文件夹中创建一个ucf文件，并且ddr3 IPS I打开了UCF文件：
# Spartan-6 SP605 Evaluation Platform
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<0> LOC=C18 | IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<1> LOC=Y6 | IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<2> LOC=W6 | IOSTANDARD=LVCMOS25;
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_pin<3> LOC=E4 | IOSTANDARD=LVCMOS15;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=L20 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=P20 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=N15 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=T22 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=P19 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=Y22 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=Y21 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=W22 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=M16 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U20 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J22 | IOSTANDARD = LVCMOS25 | TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=T8 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=U10 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T10 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AB8 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AA8 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC=R19 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC=V20 | IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=J20 | IOSTANDARD = LVCMOS25 | TIG;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_addr_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ba_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_we_n_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_cke_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<0> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<1> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<2> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<3> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<4> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<5> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<6> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<7> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<8> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<9> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<10> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<11> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<12> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<13> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<14> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dq_pin<15> IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin IOSTANDARD = DIFF_SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_udm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ldm_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_odt_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_rzq_pin IOSTANDARD = SSTL15_II;
Net fpga_0_MCB_DDR3_zio_pin IOSTANDARD = SSTL15_II;
Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net fpga_0_clk_1_sys_clk_p_pin LOC = K21 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
Net fpga_0_clk_1_sys_clk_n_pin LOC = K22 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = H8 | IOSTANDARD=LVCMOS15 | PULLUP | TIG;正如你所看到的，位流是在fpga上生成和编程的，而且当使用sdk编译和在硬件上启动时，所有的示例都工作得很好，但是当DDR3的位置不在ucf文件中时，所有的事情怎么都能正常工作？
回答 2
Stack Overflow用户
发布于 2013-06-11 03:26:36
我并不特别了解microblaze/edk设置，但我知道当我对其他组件(dcms)等使用coregen时，会为这些组件创建其他ucf文件。例如，如果我转到project_dir/ipcore_dir/，我会看到我创建的每个coregen模块都有一个单独的ucf文件。在你的项目目录中可能还有一些你看不到的其他定义文件(因为根据你的其他帖子，我假设你正在使用评估工具包)。如果你深入研究目录结构，你可能会找到它。如果您很好奇，可以尝试使用greping来查找在您的ucf文件中看到的DDR3网络名称。我敢打赌，你会找到另一个ucf，其中包含了他们在板上的引脚位置。
Stack Overflow用户
发布于 2013-06-11 05:06:27
Spartan-6使用硬连线核心块作为DDR接口。我还没有经历过UCF流，但是因为你没有得到关于引脚位置的选择，所以我并不奇怪它们根本不是S6选项。
不同的DDR存储器具有不同的电源电压，因此在那里指定IOSTANDARD是有意义的。
页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/17024476
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