键盘接口的vhdl代码
键盘接口的vhdl代码
提问于 2015-11-09 01:58:17
entity hex_kp is
Port ( row : out STD_LOGIC_VECTOR (3 downto 0);
coloumn : in STD_LOGIC_VECTOR (3 downto 0);
sevenseg : out STD_LOGIC_VECTOR (7 downto 0);
ca : out STD_LOGIC_VECTOR (3 downto 0));
end hex_kp;
architecture Behavioral of hex_kp is
begin
ca <="0111";
if(row = "0111") then
if(coloumn = "0111") then sevenseg <= "00000110" ;
elsif (coloumn = "1011") then sevenseg <= "01011011" ;
elsif (coloumn = "1101") then sevenseg <= "01001111" ;
elsif (coloumn = "1110") then sevenseg <= "01110001" ;
end if;
end if;这是我用于Basys2的4x4键盘扫描器的vhdl代码的一部分。它会给"if(row = "0111") then“语句一个错误。我不明白为什么请帮帮我。
回答 2
Stack Overflow用户
发布于 2015-11-09 02:16:16
您正尝试在并发上下文中使用if语句。但是，if语句需要在顺序上下文中-例如process语句：
process(row, column)
begin
if(row = "0111") then
if(coloumn = "0111") then
sevenseg <= "00000110";
elsif(coloumn = "1011") then
sevenseg <= "01011011";
elsif(coloumn = "1101") then
sevenseg <= "01001111";
elsif(coloumn = "1110") then
sevenseg <= "01110001";
end if;
end if;
end process;但是-请注意，如果综合以上几种情况，很可能最终会得到一组很好的闩锁(通常不需要)，因为您并没有在所有可能的情况下都赋值sevenseg (如果row不同于0111，或者如果coloumn与任何if语句都不匹配)。
要解决此问题，请1)使用时钟process，或2)如果sevenseg和row不匹配指定的情况之一，则将coloumn赋值为默认值。例如：
process(row, column)
begin
sevenseg <= (others => '0');
if(row = "0111") then
if(coloumn = "0111") then
sevenseg <= "00000110";
elsif(coloumn = "1011") then
sevenseg <= "01011011";
elsif(coloumn = "1101") then
sevenseg <= "01001111";
elsif(coloumn = "1110") then
sevenseg <= "01110001";
end if;
end if;
end process;我已经添加了sevenseg <= (others => '0');，它将使sevenseg默认为所有0，如果没有指定的案例被命中-如果命中了，它们将覆盖添加的行，并将sevenseg设置为适当的值。
一种更好的方法是使用case语句，因为这可能更好地描述了您实际需要的内容：
process(row, column)
begin
if(row = "0111") then
case coloumn is
when "0111" =>
sevenseg <= "00000110";
when "1011" =>
sevenseg <= "01011011";
when "1101" =>
sevenseg <= "01001111";
when "1110" =>
sevenseg <= "01110001";
when others =>
sevenseg <= (others => '0');
end case;
else
sevenseg <= (others => '0');
end if;
end process;Stack Overflow用户
发布于 2015-11-09 05:27:44
您可以使用条件信号赋值语句：
architecture behave of hex_kp is
begin
ca <="0111";
-- if(row = "0111") then
--
-- if(coloumn = "0111") then sevenseg <= "00000110" ;
-- elsif (coloumn = "1011") then sevenseg <= "01011011" ;
-- elsif (coloumn = "1101") then sevenseg <= "01001111" ;
-- elsif (coloumn = "1110") then sevenseg <= "01110001" ;
-- end if;
-- end if;
sevenseg <= "00000110" when coloumn = "0111" and row = "0111" else
"01011011" when coloumn = "1011" and row = "0111" else
"01001111" when coloumn = "1101" and row = "0111" else
"01110001" when coloumn = "1110" and row = "0111" else
"00000000" when row = "0111";
end architecture behave;请注意，与您的Stack Exchange问题(vhdl code interfacing keypad with fpga)一样，使用row = "0111"作为赋值条件也会导致sevenseg上的锁存。
上面的架构给出的结果与我对您的堆栈交换问题(vhdl code interfacing keypad with fpga)的回答相同。
您修改后的代码将分析、详细说明并添加模拟上述架构的测试平台：
去除锁存器就像在上面的条件信号赋值中从最终选择中删除row = "0111"一样简单，或者在Stack Exchange示例中使用case语句，为封闭的if语句提供else。
整个代码包括测试平台和两个架构，前提是使用row作为输入：
library ieee;
use ieee.std_logic_1164.all;
entity hex_kp is
port (
row: in std_logic_vector (3 downto 0);
coloumn: in std_logic_vector (3 downto 0); -- 'column 'is mispelled
sevenseg: out std_logic_vector (7 downto 0); -- why is 7 segs 8 long?
ca : out std_logic_vector (3 downto 0)
);
end entity hex_kp;
architecture behavioral of hex_kp is
-- signal row: std_logic_vector(3 downto 0); -- who drive row?
begin -- this was missing
UNLABELLED:
process(row, coloumn) -- was 'column' (didn't match declaration)
begin
ca <="0111";
if row = "0111" then
case coloumn is
when "0111" =>
sevenseg <= "00000110";
when "1011" =>
sevenseg <= "01011011";
when "1101" =>
sevenseg <= "01001111";
when "1110" =>
sevenseg <= "01110001";
when others =>
sevenseg <= (others => '0');
end case;
end if;
end process;
end architecture behavioral;
architecture behave of hex_kp is
begin
ca <="0111";
-- if(row = "0111") then
--
-- if(coloumn = "0111") then sevenseg <= "00000110" ;
-- elsif (coloumn = "1011") then sevenseg <= "01011011" ;
-- elsif (coloumn = "1101") then sevenseg <= "01001111" ;
-- elsif (coloumn = "1110") then sevenseg <= "01110001" ;
-- end if;
-- end if;
sevenseg <= "00000110" when coloumn = "0111" and row = "0111" else
"01011011" when coloumn = "1011" and row = "0111" else
"01001111" when coloumn = "1101" and row = "0111" else
"01110001" when coloumn = "1110" and row = "0111" else
"00000000" when row = "0111";
end architecture behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hex_kp_tb is
end entity;
architecture foo of hex_kp_tb is
signal row: std_logic_vector (3 downto 0);
signal coloumn: std_logic_vector (3 downto 0);
signal sevenseg: std_logic_vector (7 downto 0);
signal ca: std_logic_vector (3 downto 0);
signal count: unsigned (7 downto 0) := (others => '0');
begin
DUT:
entity work.hex_kp
port map (
row => row,
coloumn => coloumn,
sevenseg => sevenseg,
ca => ca
);
STIMULUS:
process
begin
row <= std_logic_vector (count(3 downto 0));
coloumn <= std_logic_vector (count(7 downto 4));
wait for 100 ns;
count <= count + 1;
if count = "11111111" then
wait;
end if;
end process;
end architecture;页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/33597145
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