blocks|key|1175991|text|通常，您将使用IEEE.math_real+uniform函数|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|1175992|use+IEEE.math_real.all;
procedure+UNIFORM+(variable+Seed1,Seed2:inout+integer;+variable+X:out+real);|code-block|syntax|javascript|1175993|但是稍微研究一下伪随机数生成器(PRNG)，您会发现许多变体都是简单的LFSR-它们看起来与CRC生成器非常相似。|1175994|如果您想从现有的、正在运行的PRNG开始滚动自己的PRNG，这里有几个资源：|1175995|http://www.opencores.org/?do=project&who=systemc_rng|1175996|http://verificationguild.com/modules.php?name=Downloads&d_op=viewdownload&cid=3|1175997|这是一个CRC+VHDL代码生成器：|1175998|http://www.easics.be/webtools/crctool|1175999|entityMap|0|LINK|mutability|MUTABLE|url|http://www.csee.umbc.edu/help/VHDL/stdpkg.html|1|http://en.wikipedia.org/wiki/Linear_feedback_shift_register|2|3|4^0|7|E|0|0|0|Z|4|1|0|0|0|1G|2|0|0|27|3|0|0|0|11|4|0^^$0|@$1|2|3|4|5|6|7|17|8|@]|9|@$A|18|B|19|1|1A]]|C|$]]|$1|D|3|E|5|F|7|1B|8|@]|9|@]|C|$G|H]]|$1|I|3|J|5|6|7|1C|8|@]|9|@$A|1D|B|1E|1|1F]]|C|$]]|$1|K|3|L|5|6|7|1G|8|@]|9|@]|C|$]]|$1|M|3|N|5|6|7|1H|8|@]|9|@$A|1I|B|1J|1|1K]]|C|$]]|$1|O|3|P|5|6|7|1L|8|@]|9|@$A|1M|B|1N|1|1O]]|C|$]]|$1|Q|3|R|5|6|7|1P|8|@]|9|@]|C|$]]|$1|S|3|T|5|6|7|1Q|8|@]|9|@$A|1R|B|1S|1|1T]]|C|$]]|$1|U|3|-4|5|6|7|1U|8|@]|9|@]|C|$]]]|V|$W|$5|X|Y|Z|C|$10|11]]|12|$5|X|Y|Z|C|$10|13]]|14|$5|X|Y|Z|C|$10|N]]|15|$5|X|Y|Z|C|$10|P]]|16|$5|X|Y|Z|C|$10|T]]]]

Typically you'd use the <a href="http://www.csee.umbc.edu/help/VHDL/stdpkg.html" rel="nofollow noreferrer">IEEE.math_real</a> uniform function 

<pre><code>use IEEE.math_real.all;
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);
</code></pre>

But do a tiny bit a research on pseudo random number generators (PRNGs) and you'll find many variants that are simple <a href="http://en.wikipedia.org/wiki/Linear_feedback_shift_register" rel="nofollow noreferrer">LFSR</a>'s - which look remarkably similar to CRC generators.

Here are several resources if you want to roll your own starting from existing, working PRNGs:

<a href="http://www.opencores.org/?do=project&amp;who=systemc_rng" rel="nofollow noreferrer">http://www.opencores.org/?do=project&amp;who=systemc_rng</a>

<a href="http://verificationguild.com/modules.php?name=Downloads&amp;d_op=viewdownload&amp;cid=3" rel="nofollow noreferrer">http://verificationguild.com/modules.php?name=Downloads&amp;d_op=viewdownload&amp;cid=3</a>

Here's a CRC VHDL code generator:

<a href="http://www.easics.be/webtools/crctool" rel="nofollow noreferrer">http://www.easics.be/webtools/crctool</a>

blocks|key|3839814|text|当然，Adam的随机生成器是不可合成的！您必须显式创建一个LFSR。|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|3839815|下面的例子可能会有所帮助。它是一个8位最大LFSR|3839816|module+lfsr(input+clk,+reset,+en,+output+reg+[7:0]+q);
++always+@(posedge+clk+or+posedge+reset)+begin
++++if+(reset)
++++++q+<=+8'd1;+//+can+be+anything+except+zero
++++else+if+(en)
++++++q+<=+{q[6:0],+q[7]+%5E+q[5]+%5E+q[4]+%5E+q[3]};+//+polynomial+for+maximal+LFSR
++end
endmodule;|code-block|syntax|javascript|3839817|entityMap|0|LINK|mutability|MUTABLE|url|http://en.wikipedia.org/wiki/LFSR^0|T|4|0|0|0|0^^$0|@$1|2|3|4|5|6|7|S|8|@]|9|@$A|T|B|U|1|V]]|C|$]]|$1|D|3|E|5|6|7|W|8|@]|9|@]|C|$]]|$1|F|3|G|5|H|7|X|8|@]|9|@]|C|$I|J]]|$1|K|3|-4|5|6|7|Y|8|@]|9|@]|C|$]]]|L|$M|$5|N|O|P|C|$Q|R]]]]

Of course the random generator by Adam is not synthesizable! You have to explicitly create an <a href="http://en.wikipedia.org/wiki/LFSR" rel="noreferrer">LFSR</a>.

Following example might help. It is an 8-bit maximal LFSR

<pre><code>module lfsr(input clk, reset, en, output reg [7:0] q);
 always @(posedge clk or posedge reset) begin
 if (reset)
 q &lt;= 8'd1; // can be anything except zero
 else if (en)
 q &lt;= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]}; // polynomial for maximal LFSR
 end
endmodule;
</code></pre>

blocks|key|1176051|text|上面指向OpenCores的指针在verilog文件夹中有一个名为：rng.v的文件|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|1176052|我在斯巴达-3AN上用过它，它工作得很好。在对器件进行编程后，我的代码使用随机数生成器来选择一个随机PWM，它覆盖了所有可选的PWM。|1176053|entityMap|0|LINK|mutability|MUTABLE|url|http://opencores.org/project,systemc_rng^0|Y|5|0|0|0^^$0|@$1|2|3|4|5|6|7|N|8|@]|9|@$A|O|B|P|1|Q]]|C|$]]|$1|D|3|E|5|6|7|R|8|@]|9|@]|C|$]]|$1|F|3|-4|5|6|7|S|8|@]|9|@]|C|$]]]|G|$H|$5|I|J|K|C|$L|M]]]]

The pointer above to OpenCores has a file in the verilog folder called: <a href="http://opencores.org/project,systemc_rng" rel="nofollow noreferrer">rng.v</a>

I have used it in a Spartan-3AN and it works great. My code used the random number generator to select a random PWM after I programmed the part and it covered all the selectable PWMs.

blocks|key|4682097|text|有一个在线工具，可以为伪随机数生成器生成Verilog或VHDL代码。它在OutputLogic.com上|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|4682098|entityMap|0|LINK|mutability|MUTABLE|url|http://outputlogic.com/^0|11|F|0|0^^$0|@$1|2|3|4|5|6|7|L|8|@]|9|@$A|M|B|N|1|O]]|C|$]]|$1|D|3|-4|5|6|7|P|8|@]|9|@]|C|$]]]|E|$F|$5|G|H|I|C|$J|K]]]]

There is an online tool that can generate Verilog or VHDL code for a pseudo-random number generator. It's on <a href="http://OutputLogic.com" rel="nofollow noreferrer">OutputLogic.com</a>

blocks|key|618281|text|我同意LFSR的观点。我以前做过一个，它是用于加密的。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|618282|entityMap^0|0^^$0|@$1|2|3|4|5|6|7|D|8|@]|9|@]|A|$]]|$1|B|3|-4|5|6|7|E|8|@]|9|@]|A|$]]]|C|$]]

I agree with the LFSR. I have made one before and it is used for encryption.

blocks|key|4682159|text|您已经有了一些很好的答案，但我只想指出FPGA中LFSR的规范指南在这里：|type|unstyled|depth|inlineStyleRanges|entityRanges|data|4682160|http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf|offset|length|4682161|它有一些Xilinx特有的地方(这对你的FPGA来说是可以的:)，但原理可以移植到其他地方。|4682162|entityMap|0|LINK|mutability|MUTABLE|url^0|0|0|21|0|0|0^^$0|@$1|2|3|4|5|6|7|O|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|P|8|@]|9|@$D|Q|E|R|1|S]]|A|$]]|$1|F|3|G|5|6|7|T|8|@]|9|@]|A|$]]|$1|H|3|-4|5|6|7|U|8|@]|9|@]|A|$]]]|I|$J|$5|K|L|M|A|$N|C]]]]

You've already got some good answers, but I'll just point out the canonical guide to LFSRs in FPGAs is here:

<a href="http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf" rel="nofollow noreferrer">http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf</a>

It's a bit Xilinx specific in places (which is OK for your FPGA :) but the principles are transferable to others.

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?

Random number generation on Spartan-3E

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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我需要在Spartan-3E FPGA上为我的遗传算法生成伪随机数，我想用verilog实现它:你能给我一些关于这方面的建议吗？

问Spartan-3E上的随机数生成
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