blocks|key|2309132|text|由于关注太少，Logic+Design已关闭。它现在重新开放了，但人们的兴趣仍然很低。|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|2309133|entityMap|0|LINK|mutability|MUTABLE|url|http://area51.stackexchange.com/proposals/45270/logic-design^0|7|C|0|0^^$0|@$1|2|3|4|5|6|7|L|8|@]|9|@$A|M|B|N|1|O]]|C|$]]|$1|D|3|-4|5|6|7|P|8|@]|9|@]|C|$]]]|E|$F|$5|G|H|I|C|$J|K]]]]

<a href="http://area51.stackexchange.com/proposals/45270/logic-design">Logic Design</a> was closed because of too little attention. It's now reopened, but interest remains low.

blocks|key|3716373|text|以下是摘要：|type|unstyled|depth|inlineStyleRanges|entityRanges|data|3716374|3716375|comp.arch.fpga|unordered-list-item|offset|length|3716376|comp.lang.verilog|3716377|comp.lang.vhdl|3716378|EDA+Board|3716379|Altera+Forum|3716380|Cadence+Community+Forum|3716381|Mentor+Verification+Academy+(SystemVerilog+User's+Group,+OVM/UVM)|3716382|Xilinx+Forum|3716383|Verification+Guild|3716384|EETop+(中文中，谷歌翻译是你的friend)|3716385|Sonsivri+(私有forum)|3716386|LinkedIn+(这里有多个群组)|3716387|3716388|entityMap|0|LINK|mutability|MUTABLE|url|http://groups.google.com/group/comp.arch.fpga/|1|http://groups.google.com/group/comp.lang.verilog/|2|http://groups.google.com/group/comp.lang.vhdl/|3|http://www.edaboard.com/|4|http://www.alteraforum.com/|5|http://www.cadence.com/community/forums/|6|https://verificationacademy.com/forums/systemverilog/all?sort_by=created|7|http://forums.xilinx.com/|8|http://verificationguild.com/|9|http://bbs.eetop.cn/|10|http://www.sonsivri.to/forum/index.php|11|http://www.linkedin.com/^0|0|0|0|E|0|0|0|H|1|0|0|E|2|0|0|9|3|0|0|C|4|0|0|N|5|0|0|1T|6|0|0|C|7|0|0|I|8|0|0|5|9|0|0|8|A|0|0|8|B|0|0^^$0|@$1|2|3|4|5|6|7|1Y|8|@]|9|@]|A|$]]|$1|B|3|-4|5|6|7|1Z|8|@]|9|@]|A|$]]|$1|C|3|D|5|E|7|20|8|@]|9|@$F|21|G|22|1|23]]|A|$]]|$1|H|3|I|5|E|7|24|8|@]|9|@$F|25|G|26|1|27]]|A|$]]|$1|J|3|K|5|E|7|28|8|@]|9|@$F|29|G|2A|1|2B]]|A|$]]|$1|L|3|M|5|E|7|2C|8|@]|9|@$F|2D|G|2E|1|2F]]|A|$]]|$1|N|3|O|5|E|7|2G|8|@]|9|@$F|2H|G|2I|1|2J]]|A|$]]|$1|P|3|Q|5|E|7|2K|8|@]|9|@$F|2L|G|2M|1|2N]]|A|$]]|$1|R|3|S|5|E|7|2O|8|@]|9|@$F|2P|G|2Q|1|2R]]|A|$]]|$1|T|3|U|5|E|7|2S|8|@]|9|@$F|2T|G|2U|1|2V]]|A|$]]|$1|V|3|W|5|E|7|2W|8|@]|9|@$F|2X|G|2Y|1|2Z]]|A|$]]|$1|X|3|Y|5|E|7|30|8|@]|9|@$F|31|G|32|1|33]]|A|$]]|$1|Z|3|10|5|E|7|34|8|@]|9|@$F|35|G|36|1|37]]|A|$]]|$1|11|3|12|5|E|7|38|8|@]|9|@$F|39|G|3A|1|3B]]|A|$]]|$1|13|3|-4|5|6|7|3C|8|@]|9|@]|A|$]]|$1|14|3|-4|5|6|7|3D|8|@]|9|@]|A|$]]]|15|$16|$5|17|18|19|A|$1A|1B]]|1C|$5|17|18|19|A|$1A|1D]]|1E|$5|17|18|19|A|$1A|1F]]|1G|$5|17|18|19|A|$1A|1H]]|1I|$5|17|18|19|A|$1A|1J]]|1K|$5|17|18|19|A|$1A|1L]]|1M|$5|17|18|19|A|$1A|1N]]|1O|$5|17|18|19|A|$1A|1P]]|1Q|$5|17|18|19|A|$1A|1R]]|1S|$5|17|18|19|A|$1A|1T]]|1U|$5|17|18|19|A|$1A|1V]]|1W|$5|17|18|19|A|$1A|1X]]]]

Here is a summary:
<ul>
<li><a href="http://groups.google.com/group/comp.arch.fpga/" rel="nofollow noreferrer">comp.arch.fpga</a></li>
<li><a href="http://groups.google.com/group/comp.lang.verilog/" rel="nofollow noreferrer">comp.lang.verilog</a></li>
<li><a href="http://groups.google.com/group/comp.lang.vhdl/" rel="nofollow noreferrer">comp.lang.vhdl</a></li>
<li><a href="http://www.edaboard.com/" rel="nofollow noreferrer">EDA Board</a></li>
<li><a href="http://www.alteraforum.com/" rel="nofollow noreferrer">Altera Forum</a></li>
<li><a href="http://www.cadence.com/community/forums/" rel="nofollow noreferrer">Cadence Community Forum</a></li>
<li><a href="https://verificationacademy.com/forums/systemverilog/all?sort_by=created" rel="nofollow noreferrer">Mentor Verification Academy (SystemVerilog User's Group, OVM/UVM)</a></li>
<li><a href="http://forums.xilinx.com/" rel="nofollow noreferrer">Xilinx Forum</a></li>
<li><a href="http://verificationguild.com/" rel="nofollow noreferrer">Verification Guild</a></li>
<li><a href="http://bbs.eetop.cn/" rel="nofollow noreferrer">EETop</a> (in Chinese, Google translate is your friend)</li>
<li><a href="http://www.sonsivri.to/forum/index.php" rel="nofollow noreferrer">Sonsivri</a> (private forum)</li>
<li><a href="http://www.linkedin.com" rel="nofollow noreferrer">LinkedIn</a> (there are a number of groups here)</li>
</ul>

blocks|key|671329|text|IRC:+irc.freenode.net上的##verilog，##vhdl，##fpga|type|unstyled|depth|inlineStyleRanges|entityRanges|data|671330|网络新闻:+comp.arch.fpga+(http://groups.google.com/group/comp.arch.fpga/topics)|offset|length|671331|entityMap|0|LINK|mutability|MUTABLE|url|http://groups.google.com/group/comp.arch.fpga/topics^0|0|M|1G|0|0^^$0|@$1|2|3|4|5|6|7|N|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|O|8|@]|9|@$D|P|E|Q|1|R]]|A|$]]|$1|F|3|-4|5|6|7|S|8|@]|9|@]|A|$]]]|G|$H|$5|I|J|K|A|$L|M]]]]

IRC: ##verilog, ##vhdl, ##fpga on irc.freenode.net

Netnews: comp.arch.fpga (<a href="http://groups.google.com/group/comp.arch.fpga/topics" rel="nofollow noreferrer">http://groups.google.com/group/comp.arch.fpga/topics</a>)

blocks|key|673156|text|comp.lang.vhdl|type|unstyled|depth|inlineStyleRanges|entityRanges|data|673157|http://groups.google.com/group/comp.lang.vhdl/|offset|length|673158|我已经有几年没有积极地阅读它了，但我记得它是一个很好的来源，有一些非常有见识和帮助的人。现在看来，它似乎收到了很多垃圾邮件，这是不幸的。|673159|entityMap|0|LINK|mutability|MUTABLE|url^0|0|0|1A|0|0|0^^$0|@$1|2|3|4|5|6|7|O|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|P|8|@]|9|@$D|Q|E|R|1|S]]|A|$]]|$1|F|3|G|5|6|7|T|8|@]|9|@]|A|$]]|$1|H|3|-4|5|6|7|U|8|@]|9|@]|A|$]]]|I|$J|$5|K|L|M|A|$N|C]]]]

comp.lang.vhdl

<a href="http://groups.google.com/group/comp.lang.vhdl/" rel="nofollow noreferrer">http://groups.google.com/group/comp.lang.vhdl/</a>

I haven't actively read it in a couple years, but I recall it being a great source, with some very knowledgeable and helpful people. Looking at it now it appears to be getting a lot of spam, which is unfortunate.

blocks|key|2309108|text|Xilinx和Altera+FPGA论坛讨论在FPGA中使用Verilog/VHDL语言的不同方面。|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|2309109|entityMap|0|LINK|mutability|MUTABLE|url|http://forums.xilinx.com/^0|0|6|0|0^^$0|@$1|2|3|4|5|6|7|L|8|@]|9|@$A|M|B|N|1|O]]|C|$]]|$1|D|3|-4|5|6|7|P|8|@]|9|@]|C|$]]]|E|$F|$5|G|H|I|C|$J|K]]]]

<a href="http://forums.xilinx.com/" rel="nofollow noreferrer">Xilinx</a> and Altera FPGA forums deal with different aspects of using Verilog/VHDL for FPGAs.

blocks|key|3716172|text|Verification+Guild论坛使用Verilog/VHDL/SystemVerilog处理硬件设计验证。|type|unstyled|depth|inlineStyleRanges|offset|length|style|BOLD|entityRanges|data|3716173|更新:我最近发现的另一个论坛是：edaboard.com|3716174|entityMap|0|LINK|mutability|MUTABLE|url|http://verificationguild.com/|1|http://www.edaboard.com/^0|1I|2|0|I|0|0|G|C|1|0^^$0|@$1|2|3|4|5|6|7|R|8|@$9|S|A|T|B|C]]|D|@$9|U|A|V|1|W]]|E|$]]|$1|F|3|G|5|6|7|X|8|@]|D|@$9|Y|A|Z|1|10]]|E|$]]|$1|H|3|-4|5|6|7|11|8|@]|D|@]|E|$]]]|I|$J|$5|K|L|M|E|$N|O]]|P|$5|K|L|M|E|$N|Q]]]]

The <a href="http://verificationguild.com" rel="nofollow noreferrer">Verification Guild</a> forum deals with hardware design verification with Verilog/VHDL/SystemVerilog.

Update:
Another forum I discovered recently is: <a href="http://www.edaboard.com" rel="nofollow noreferrer">edaboard.com</a>

blocks|key|1415991|text|Verilog新闻集团：http://www.rhinocerus.net/forum/lang-verilog/|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|1415992|entityMap|0|LINK|mutability|MUTABLE|url|http://www.rhinocerus.net/forum/lang-verilog/^0|C|19|0|0^^$0|@$1|2|3|4|5|6|7|L|8|@]|9|@$A|M|B|N|1|O]]|C|$]]|$1|D|3|-4|5|6|7|P|8|@]|9|@]|C|$]]]|E|$F|$5|G|H|I|C|$J|K]]]]

Verilog News Group:
<a href="http://www.rhinocerus.net/forum/lang-verilog/" rel="nofollow">http://www.rhinocerus.net/forum/lang-verilog/</a>

blocks|key|2309196|text|从FPGA%7CDSP%7Cembeddedrelated.com页面：www.fpgarelated.com/|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|2309197|entityMap|0|LINK|mutability|MUTABLE|url|http://www.fpgarelated.com/^0|W|K|0|0^^$0|@$1|2|3|4|5|6|7|L|8|@]|9|@$A|M|B|N|1|O]]|C|$]]|$1|D|3|-4|5|6|7|P|8|@]|9|@]|C|$]]]|E|$F|$5|G|H|I|C|$J|K]]]]

From the [FPGA|DSP|embedded]related.com pages: <a href="http://www.fpgarelated.com/" rel="nofollow">www.fpgarelated.com/</a>

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming.

Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC?

VHDL/Verilog related programming forums?

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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如今，用VHDL或Verilog进行硬件设计更像是编程。然而，我看到大家对VHDL/Verilog编程的讨论并不是那么积极。有没有用Verilog/VHDL/SystemVerilog或SystemC进行硬件设计的论坛？

问VHDL/Verilog相关编程论坛？
EN

回答 8

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问VHDL/Verilog相关编程论坛？EN

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问VHDL/Verilog相关编程论坛？
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