blocks|key|3893452|text|我认为是有的；一个线程块被分配给一个流式多处理器(+SM+)，SM进一步将每个块的线程划分为32个线程(较新的体系结构可以处理更大的warps)，这些线程被调度为按顺序(多-少)执行。考虑到这一点，将每个计算分成块会更快，以便它们占用尽可能多的SMs。构建是卡支持的每个经线的线程的倍数的块也意味着已满(对于SMs使用32线程经线的情况，是32或64个线程的块，而不是40个线程的块)。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|3893453|entityMap^0|0^^$0|@$1|2|3|4|5|6|7|D|8|@]|9|@]|A|$]]|$1|B|3|-4|5|6|7|E|8|@]|9|@]|A|$]]]|C|$]]

I think there is; A thread block is assigned to a Streaming Multiprocessor (SM) and the SM further divides the threads of each block into warps of 32 threads (newer architectures can handle larger warps) that are scheduled to be executed (more-less) sequentially. Considering this, it will be faster to break each computation into blocks so that they occupy as many SMs as possible. It is also meaning full to build blocks that are multiples of the threads per warp that the card supports (a block of 32 or 64 threads rather than 40 threads, for the case that SMs use 32-thread warps).

blocks|key|2167689|text|启动延迟|type|unstyled|depth|inlineStyleRanges|offset|length|style|BOLD|entityRanges|data|2167690|启动延迟(对工作的API调用在GPU上启动)是一个网格，在Linux上为3-8µs，在Windows+Vista/Win7上为30-80µs。|2167691|将数据块分发到SM的时间为10-100s+ns。|2167692|在一个块(32个线程)中启动一个warp需要几个周期，并且在每个SM上并行发生。|2167693|资源限制|2167694|并发内核-特斯拉N/A一次仅1个网格-费米16个网格-开普勒16个网格(Kepler2+32个网格)|2167695|最大块数(不考虑占用限制)-+Tesla+SmCount+*8+(gtx280+=+30+*8=+240)+-费米SmCount+*+16+(gf100+=+16+*+16+=+256)+-开普勒SmCount+*+16+(gk104+=8*+16+=+128)|2167696|请参阅占用计算器，了解每个块的线程、每个SM的线程、每个SM的寄存器、每个线程的寄存器的限制。|2167697|Warps调度和Cores|2167698|CUDA核心是浮点/ALU单元。每个SM都有其他类型的执行单元，包括加载/存储、特殊功能、分支等。CUDA核心相当于x86处理器中的单指令多路复用单元。它不等同于x86核心。|2167699|占用率是衡量每个SM的翘曲数到每个SM的最大翘曲数的指标。每SM的warp越多，则warp调度器具有合格的warp进行调度的机会越高。但是，占用率越高，每个线程可用的资源就越少。作为一个基本目标，你想要达到的目标不仅仅是|2167700|特斯拉上的25%25+8次翘曲50%25费米上的24次翘曲50%25或开普勒上的32次翘曲(通常更高)|2167701|您将注意到，在这些计算中与CUDA核心没有真正的关系。|2167702|为了更好地理解这一点，请阅读Fermi白皮书，如果您可以使用Nsight+Visual+Studio+Edition+CUDA+Profiler，请查看问题效率实验(+CUDA+Profiler或Visual+Profiler中尚未提供)，以了解您的内核隐藏执行和内存延迟的情况。|2167703|entityMap^0|0|4|0|0|0|0|0|4|0|0|0|0|0|D|0|0|0|0|0|0^^$0|@$1|2|3|4|5|6|7|17|8|@$9|18|A|19|B|C]]|D|@]|E|$]]|$1|F|3|G|5|6|7|1A|8|@]|D|@]|E|$]]|$1|H|3|I|5|6|7|1B|8|@]|D|@]|E|$]]|$1|J|3|K|5|6|7|1C|8|@]|D|@]|E|$]]|$1|L|3|M|5|6|7|1D|8|@$9|1E|A|1F|B|C]]|D|@]|E|$]]|$1|N|3|O|5|6|7|1G|8|@]|D|@]|E|$]]|$1|P|3|Q|5|6|7|1H|8|@]|D|@]|E|$]]|$1|R|3|S|5|6|7|1I|8|@]|D|@]|E|$]]|$1|T|3|U|5|6|7|1J|8|@$9|1K|A|1L|B|C]]|D|@]|E|$]]|$1|V|3|W|5|6|7|1M|8|@]|D|@]|E|$]]|$1|X|3|Y|5|6|7|1N|8|@]|D|@]|E|$]]|$1|Z|3|10|5|6|7|1O|8|@]|D|@]|E|$]]|$1|11|3|12|5|6|7|1P|8|@]|D|@]|E|$]]|$1|13|3|14|5|6|7|1Q|8|@]|D|@]|E|$]]|$1|15|3|-4|5|6|7|1R|8|@]|D|@]|E|$]]]|16|$]]

Launch Latency

Launch latency (API call to work is started on the GPU) is of a grid is 3-8 µs on Linux to
 30-80 µs on Windows Vista/Win7.

Distributing a block to a SM is 10-100s ns.

Launching a warp in a block (32 threads) is a few cycles and happens in parallel on each SM.

Resource Limitations

Concurrent Kernels
- Tesla N/A only 1 grid at a time
- Fermi 16 grids at a time
- Kepler 16 grids (Kepler2 32 grids)

Maximum Blocks (not considering occupancy limitations)
- Tesla SmCount * 8 (gtx280 = 30 * 8 = 240)
- Fermi SmCount * 16 (gf100 = 16 * 16 = 256)
- Kepler SmCount * 16 (gk104 = 8 * 16 = 128)

See occupancy calculator for limitations on threads per block, threads per SM, registers per SM, registers per thread, ...

Warps Scheduling and CUDA Cores

CUDA cores are floating point/ALU units. Each SM has other types of execution units including load/store, special function, branch, etc. A CUDA core is equivalent to a SIMD unit in a x86 processor. It is not equivalent to a x86 core.

Occupancy is the measure of warps per SM to the maximum number of warps per SM. The more warps per SM the higher the chance that the warp scheduler has an eligible warp to schedule. However, the higher the occupancy the less resources will be available per thread. As a basic goal you want to target more than

25% 8 warps on Tesla
50% or 24 warps on Fermi
50% or 32 warps on Kepler (generally higher)

You'll notice there is no real relationship to CUDA cores in these calculations.

To understand this better read the Fermi whitepaper and if you can use the Nsight Visual Studio Edition CUDA Profiler look at the Issue Efficiency Experiment (not yet available in the CUDA Profiler or Visual Profiler) to understand how well your kernel is hiding execution and memory latency.

Can there be any performance advantage to launch a grid of blocks simultaneously over launching blocks one at a time if the number of threads in each block is already larger than the number of CUDA cores?

optimal number of CUDA parallel blocks

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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如果每个块中的线程数量已经超过CUDA核心的数量，那么同时启动一个块网格与一次启动一个块相比，是否有任何性能优势？

问CUDA并行块的最佳数量
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