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社区首页 >问答首页 >错误(10395):VHDL条件信号赋值错误:条件波形必须具有相同数量的元素

错误(10395):VHDL条件信号赋值错误:条件波形必须具有相同数量的元素
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Stack Overflow用户
提问于 2019-08-13 21:10:37
回答 1查看 549关注 0票数 0

错误(10395):vga.vhd处的VHDL条件信号赋值错误(146.):条件波形必须具有相同数量的元素。在此行中显示错误

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R<=intensity WHEN red_switch='0' AND dena='1' ELSE (OTHERS=>'1');

我真的不知道什么是错误的vhdl Altera代码错误,但它没有解决我的问题。提前谢谢。

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 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_arith.all;
 LIBRARY lpm;
 USE lpm.lpm_components.all;
 ----------------------------------------------------------
 ENTITY vga IS
 GENERIC (
 Ha: INTEGER := 96; --Hpulse
 Hb: INTEGER := 144; --Hpulse+HBP
 Hc: INTEGER := 784; --Hpulse+HBP+Hactive
 Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP
 Va: INTEGER := 2; --Vpulse
 Vb: INTEGER := 35; --Vpulse+VBP
 Vc: INTEGER := 515; --Vpulse+VBP+Vactive
 Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP
 PORT (
 clk: IN STD_LOGIC; --50MHz in our board
 red_switch, green_switch, blue_switch: IN STD_LOGIC;
 pixel_clk: BUFFER STD_LOGIC;
 Hsync, Vsync: BUFFER STD_LOGIC;
 R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 nblanck, nsync : OUT STD_LOGIC);
 END vga;
 ----------------------------------------------------------
 ARCHITECTURE vga OF vga IS
 SIGNAL Hactive, Vactive, dena: STD_LOGIC;
 SIGNAL address: STD_LOGIC_VECTOR(8 DOWNTO 0);
 SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0);
 BEGIN
 -------------------------------------------------------
 --Part 1: CONTROL GENERATOR
 -------------------------------------------------------
 --Static signals for DACs:
 nblanck <= '1'; --no direct blanking
 nsync <= '0'; --no sync on green
 --Create pixel clock (50MHz->25MHz):
 PROCESS (clk)
 BEGIN
 IF (clk'EVENT AND clk='1') THEN
 pixel_clk <= NOT pixel_clk;
 END IF;
 END PROCESS;
 --Horizontal signals generation:
 PROCESS (pixel_clk)
 VARIABLE Hcount: INTEGER RANGE 0 TO Hd;
 BEGIN
 IF (pixel_clk'EVENT AND pixel_clk='1') THEN
 Hcount := Hcount + 1;
 IF (Hcount=Ha) THEN
 Hsync <= '1';
 ELSIF (Hcount=Hb) THEN
 Hactive <= '1';
 ELSIF (Hcount=Hc) THEN
 Hactive <= '0';
 ELSIF (Hcount=Hd) THEN
 Hsync <= '0';
 Hcount := 0;
 END IF;
 END IF;
  END PROCESS;
 --Vertical signals generation:
 PROCESS (Hsync)
 VARIABLE Vcount: INTEGER RANGE 0 TO Vd;
 BEGIN
 IF (Hsync'EVENT AND Hsync='0') THEN
 Vcount := Vcount + 1;
 IF (Vcount=Va) THEN
 Vsync <= '1';
 ELSIF (Vcount=Vb) THEN
 Vactive <= '1';
 ELSIF (Vcount=Vc) THEN
 Vactive <= '0';
 ELSIF (Vcount=Vd) THEN
 Vsync <= '0';
 Vcount := 0;
 END IF;
 END IF;
 END PROCESS;
 ---Display enable generation:
 dena <= Hactive AND Vactive;
 -------------------------------------------------------
 --Part 2: IMAGE GENERATOR
 -------------------------------------------------------
     PROCESS (Hsync, Vsync, Vactive, dena, red_switch,
     green_switch, blue_switch)
     VARIABLE line_counter: INTEGER RANGE 0 TO Vc;
     BEGIN
     IF (Vsync='0') THEN
     line_counter := 0;
     ELSIF (Hsync'EVENT AND Hsync='1') THEN
     IF (Vactive='1') THEN
     line_counter := line_counter + 1;
     END IF;
     END IF;
     IF (dena='1') THEN
     IF (line_counter=1) THEN
     R <= (OTHERS => '1');
     G <= (OTHERS => '0');
     B <= (OTHERS => '0');
     ELSIF (line_counter>1 AND line_counter<=3) THEN
     R <= (OTHERS => '0');
     G <= (OTHERS => '1');
      B <= (OTHERS => '0');
     ELSIF (line_counter>3 AND line_counter<=6) THEN
     R <= (OTHERS => '0');
     G <= (OTHERS => '0');
     B <= (OTHERS => '1');
     ELSE
     R <= (OTHERS => red_switch);
     G <= (OTHERS => green_switch);
     B <= (OTHERS => blue_switch);
     END IF;
    ELSE
     R <= (OTHERS => '0');
     G <= (OTHERS => '0');
     B <= (OTHERS => '0');
     END IF;
     END PROCESS;
--END vga;
 -------------------------------------------
 --ROM instantiation:
 myrom: lpm_rom
 GENERIC MAP (
 lpm_widthad => 9, --address width
 lpm_outdata => "UNREGISTERED",
 lpm_address_control => "REGISTERED",
 lpm_file => "pic_6.mif", --data file
 lpm_width => 10) --data width
 PORT MAP (
 inclock=>NOT pixel_clk, address=>address, q=>intensity);
 --Create address (row number):
 PROCESS (Vsync, Hsync)
 VARIABLE line_counter: INTEGER RANGE 0 TO Vd;
 BEGIN
 IF (Vsync='0') THEN
 line_counter := 0;
 ELSIF (Hsync'EVENT AND Hsync='1') THEN
 IF (Vactive='1') THEN
 line_counter := line_counter + 1;
 END IF;
 END IF;
 address <= conv_std_logic_vector(line_counter, 9);
 END PROCESS;
-- --Assign color values to R/G/B:
 R<=intensity WHEN red_switch='0' AND dena='1' ELSE (OTHERS=>'1');
 G<=intensity WHEN green_switch='0' AND dena='1' ELSE (OTHERS=>'1');
 B<=intensity WHEN blue_switch='0' AND dena='1' ELSE (OTHERS=>'1');
 END vga;
EN

Stack Overflow用户

发布于 2019-08-13 21:22:35

信号R为8位宽:

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R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

当信号intensity为10位宽时:

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SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0);

这在VHDL中是不允许的。两者必须具有相同的宽度;您必须显式截断intensity或扩展R

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页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接:

https://stackoverflow.com/questions/57478436

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