Verilog计数器总是阻塞不起作用
Verilog计数器总是阻塞不起作用
提问于 2020-11-15 18:43:19
我在使用以下代码的PC部分时遇到问题。它应该从0开始计数，但是当我运行testbench文件时，它不会计数。我和TA谈过了，我不明白为什么testbench文件没有计算PC寄存器。当我运行testbench文件时，PC以某种方式输出了一些无用的值。有人能帮我弄清楚为什么它不工作吗？
# 0TEST MY DESIGN
# 0Address bus: x, STR Data : x, LDR Data : x, Read: x, Write: x, PC: x, Reset is x
# 2Address bus: x, STR Data : x, LDR Data : x, Read: 0, Write: 0, PC: x, Reset is 0
# 6Address bus: x, STR Data : x, LDR Data : x, Read: 0, Write: 0, PC: x, Reset is 1
# 11Address bus: 10, STR Data : x, LDR Data : 7, Read: 1, Write: 0, PC: x, Reset is 1
# 21Address bus: 7, STR Data : 2, LDR Data : 7, Read: 0, Write: 1, PC: x, Reset is 1
# 31Address bus: 10, STR Data : 2, LDR Data : 9, Read: 1, Write: 0, PC: x, Reset is 1
# 41Address bus: 9, STR Data : 7, LDR Data : 9, Read: 0, Write: 1, PC: x, Reset is 1
# 51Address bus: x, STR Data : 7, LDR Data : 9, Read: 0, Write: 0, PC: x, Reset is 1代码：
module MemoryControl
(
Clk,PC,Reset,Result,source1,source2,opcode,LDR_EN,Address_EN,AddBus,DataBus_L,DataBus_S,LDRin,R,W
);
/*Variable*/
input [31:0] Result,source1,source2,DataBus_L;
input [3:0] opcode;
input Clk,Reset;
output reg LDR_EN, Address_EN;
output reg [31:0]PC,LDRin,AddBus,DataBus_S;
output reg R,W;
/*PC Count Always Block. PC counts from 0 to 16*/
always@(posedge Clk)
begin
if (!Reset)
PC = 0;
else PC = PC + 1;
end
/*LDR MUX Always Block opcode 4'b1110*/
always@*
begin
if (opcode == 4'b1110)
begin
LDR_EN = 1;
Address_EN = 1;
R = 1; W = 0;
/*Address Mux LDR data fetch*/
case (Address_EN)
0: AddBus = PC;
1: AddBus = source1;
default: AddBus = 0;
endcase
/*Fetched LDR data outputs to register bank*/
case (LDR_EN)
1: LDRin = DataBus_L;
0: LDRin = Result;
default: LDRin = 0;
endcase
end
end
/*STR MUX Always Block opcode 1101*/
always@*
begin
if (opcode == 4'b1101)
begin
Address_EN = 1;
DataBus_S = source2;
W = 1; R = 0;
case (Address_EN)
0: AddBus = PC;
1: AddBus = source1;
default: AddBus = 0;
endcase
end
end
/*Fetch Instruction from PC when not STR or LDR*/
always@*
begin
if (opcode == !4'b1110 && opcode == !4'b1101)
begin
Address_EN = 0;
R = 0; W = 0;
case (Address_EN)
0: AddBus = PC;
1: AddBus = source1;
default: AddBus = 0;
endcase
end
end
endmodule下面的模块是上述Verilog文件的testbench文件。
module MemoryContro_t;
reg [31:0] Result_t,source1_t,source2_t,DataBus_L_t;
reg [3:0] opcode_t;
reg Clk_t,Reset_t;
wire LDR_EN_t, Address_EN_t;
wire [31:0]PC_t, AddBus_t,DataBus_S_t,LDRin_t;
wire R_t,W_t;
initial begin
$display($time,"TEST MY DESIGN");
#2 Result_t=0; source1_t=0; source2_t=0; DataBus_L_t = 0; opcode_t=0; Reset_t = 0;
#4 Reset_t = 1;
#5 Result_t=0; source1_t=10; source2_t=5; DataBus_L_t = 7; opcode_t=4'b1110; // LDR Test ,LDR Data initialized
#10 Result_t=0; source1_t=7; source2_t=2; DataBus_L_t = 6; opcode_t=4'b1101; // STR Test ,STR Data initialized
#10 Result_t=0; source1_t=10; source2_t=5; DataBus_L_t = 9; opcode_t=4'b1110; // LDR Test ,LDR Data overwritten
#10 Result_t=0; source1_t=9; source2_t=7; DataBus_L_t = 10; opcode_t=4'b1101; // STR Test ,STR Data overwritten
#10 Result_t=0; source1_t=9; source2_t=7; DataBus_L_t = 10; opcode_t=!4'b1101&&4'b1110; // PC TEST
end
always #5 Clk_t=~Clk_t;
initial begin
$monitor($time,"Address bus: %d, STR Data : %d, LDR Data : %d, Read: %d, Write: %d, PC: %d, Reset is %d", AddBus_t, DataBus_S_t,LDRin_t,R_t,W_t,PC_t, Reset_t);
end
MemoryControl MUT (.Clk(Clk_t),.PC(PC_t),.Reset(Reset_t),.Result(Result_t),.source1(source1_t),.source2(source2_t),.opcode(opcode_t),
.LDR_EN(LDR_EN_t),.Address_EN(Address_EN_t),.AddBus(AddBus_t),.DataBus_L(DataBus_L_t),.DataBus_S(DataBus_S_t),.LDRin(LDRin_t),.R(R_t),.W(W_t));
endmodule回答 2
Stack Overflow用户
发布于 2020-11-15 19:46:00
您需要在testbench模块中初始化时钟信号。您将其声明为reg，这意味着它的初始值是X(未知)。
initial Clk_t = 0;在整个模拟过程中，它始终保持为X，这意味着PC值永远不会增加，因为不会触发always@(posedge Clk)。
如果您没有使用波形调试您的模拟，则应该这样做。当我看着waves时，我立即注意到了这个问题。
Stack Overflow用户
发布于 2020-11-15 20:57:14
- 时钟没有初始值，您可以使用以下样式设置它: reg Clk_t = 1'b0 ;
- 您的DUT中的重置是低电平有效，因此在TB中，您应该将Result_t设置为0，然后将其设置为1。
页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/64843453
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