问ChiselTest:将有符号整型转换为无符号整型，以获得期望值

EN

    test(new ALU) { c =>
    ...
        /* Sub */
        c.io.ctl.poke(Control.ALU_SUB)
        c.io.src0.poke(4321.U)
        c.io.src1.poke(1234.U)
        c.io.out.expect(3087.U)
        c.io.src0.poke(1234.U)
        c.io.src1.poke(4321.U)
        c.io.out.expect("b_1111_0011_1111_0001".U) /* 2's compliment */
    }

test(new ALU) { c =>
    /* Sub */
    c.io.ctl.poke(Control.ALU_SUB)
    c.io.src0.poke(4321.U)
    c.io.src1.poke(1234.U)
    c.io.out.expect(3087.U)
    c.io.src0.poke(1234.U)
    c.io.src1.poke(4321.U)
    c.io.out.expect(-3087.S.asUInt)
}

[error] (run-main-9) chisel3.internal.ChiselException: Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox.
[error] chisel3.internal.ChiselException: Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox.
[error]         at chisel3.internal.throwException$.apply(Error.scala:85)
[error]         at chisel3.internal.Builder$.forcedUserModule(Builder.scala:298)
[error]         at chisel3.internal.Builder$.pushOp(Builder.scala:336)
[error]         at chisel3.SInt.do_asUInt(Bits.scala:925)
[error]         at cpu.alu$.$anonfun$new$2(Main.scala:26)
[error]         at cpu.alu$.$anonfun$new$2$adapted(Main.scala:18)
[error]         at chiseltest.backends.treadle.TreadleBackend.$anonfun$run$1(TreadleBackend.scala:144)
[error]         at chiseltest.internal.ThreadedBackend$TesterThread$$anon$1.$anonfun$run$1(ThreadedBackend.scala:453)
[error]         at chiseltest.backends.treadle.TreadleBackend.doTimescope(TreadleBackend.scala:103)
[error]         at chiseltest.internal.ThreadedBackend$TesterThread$$anon$1.run(ThreadedBackend.scala:453)
[error]         at java.lang.Thread.run(Thread.java:748)
[error] stack trace is suppressed; run last Test / bgRunMain for the full output
[error] Nonzero exit code: 1
[error] (Test / runMain) Nonzero exit code: 1

class ALU extends Module {
  val io = IO(new Bundle {
    val ctl   = Input(UInt(Control.ALU_BITWIDTH))
    val src0  = Input(UInt(Instructions.WORD_SIZE.W))
    val src1  = Input(UInt(Instructions.WORD_SIZE.W))
    val out   = Output(UInt(Instructions.WORD_SIZE.W))
  })

  val shift = io.src1(3,0).asUInt

  /* Lookup the operation to execute */
  io.out := MuxLookup(io.ctl, 0.U, Seq(
    Control.ALU_ADD -> (io.src0 + io.src1),
    Control.ALU_SUB -> (io.src0 - io.src1),
    Control.ALU_AND -> (io.src0 & io.src1),
    Control.ALU_OR  -> (io.src0 | io.src1),
    Control.ALU_XOR -> (io.src0 ^ io.src1),
    Control.ALU_NOT -> (~io.src0),
    Control.ALU_SLL -> (io.src0 << shift),
    Control.ALU_SRL -> (io.src0 >> shift),
  ))
}