问您能在systemverilog文件中导入vhdl包吗？

EN

    library ieee;
    use ieee.std_logic_1164.all;

    -- FILE: my_pkg.vhd
    package my_pkg is

      type type1 is record
        sig2 : std_logic;
        vec1 : std_logic_vector(7 downto 0);
      end record;  

    end package;

// FILE: testbench.sv
import my_pkg::*;

module testbench;

type1 sigtype1;

initial begin
    sigtype1.sig2 = 1'b1;
    sigtype1.vec1 = 8'hA;
    $finish(2);
end

endmodule

    // FILE: my_pkg.sv
    package my_pkg;

      typedef struct packed {
        bit       sig2;
        bit [7:0] vec1;
      };

    endpackage;

C:\questasim64_2020.4\win64\vcom.exe -2002 -l simout.vhdl.log 
-work work ./hdl/my_pkg.vhd
QuestaSim-64 vcom 2020.4 Compiler 2020.10 Oct 13 2020
Start time: 11:39:52 on Jan 19,2022
vcom -2002 -l simout.vhdl.log -work work ./hdl/my_pkg.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling package my_pkg
End time: 11:39:52 on Jan 19,2022, Elapsed time: 0:00:00
Errors: 0, Warnings: 0
ok

C:\questasim64_2020.4\win64\vlog.exe -work work -l simout.vlog.log 
./hdl/testbench.sv

QuestaSim-64 vlog 2020.4 Compiler 2020.10 Oct 13 2020

Start time: 11:39:52 on Jan 19,2022

vlog -work work -l simout.vlog.log ./hdl/testbench.sv

** Error: 
C:/Users/wpmoore/Desktop/collins/sandbox/sandbox.try1/hdl/testbench.sv(
2): (vlog-13006) Could not find the package (my_pkg).  Design read will 
continue, but expect a cascade of errors after this failure.  
Furthermore if you experience a vopt-7 error immediately before this 
error then please check the package names or the library search paths 
on the command line.
End time: 11:39:52 on Jan 19,2022, Elapsed time: 0:00:00

Errors: 1, Warnings: 0