将MMIO外设作为子模块添加到火箭芯片中
将MMIO外设作为子模块添加到火箭芯片中
提问于 2022-02-23 13:15:51
我遵循Chipyard文档中的MMIO外设页面，学习如何在Chipyard框架内向火箭芯片中添加模块--所有这些似乎都运行得很好。我总结了自己的经历，并试图在“纽约时报”( 凿子学习历程 <== )的页面上以较慢的速度写出来，并补充道，只有当回答问题的人想看一看，看看我的一切是否正常运行时，我才会这样写。换句话说，我在Chipyard的example包中添加了MMIO，它编译、生成模拟器、正确响应我设计的玩具基准，我甚至在gtkwave中看到了相应的波形。
现在，我想要采取的下一步是将这个虚拟设计(它只是从存储硬编码值的内存映射寄存器中读取)从芯片/火箭芯片基础结构中分离出来，因为它位于一个单独的回购中，这将成为我芯片厂的一个子模块。因此，为了做到这一点，我从此页开始并采取了所有步骤，如下所示：
- 创建了一个新的回购程序，名为
my-chip - 在
my-chip中，我添加了以下内容的build.sbt：
organization := "My Chip"
version := "1.0"
name := "my-chip"
scalaVersion := "2.12.10"- 在
my-chip中，我添加了src/main/scala/JustRead.scala，它是通过上述学习之旅页面构建的 - 在JustRead.scala中，我只替换了
package行，所以现在它是：
package my-chip- 然后，我将
my-chip回购作为子模块添加到path：chipyard/generators/my-chip - 最后，我将适当的行添加到
chipyard/generators/chipyard/src/main/scala/DigitalTop.scala，如下所示：
package chipyard
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------
// BOOM and/or Rocket Top Level Systems
// ------------------------------------
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends System
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with my-chip.CanHavePeripheryJustRead // <=== ADDED THIS LINE
with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
with icenet.CanHavePeripheryIceNICModuleImp
with chipyard.example.CanHavePeripheryGCDModuleImp
with my-chip.CanHavePeripheryJustReadTopModuleImp // <=== AND THIS LINE
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop- 然后，我按照以下方式在
chipyard/generators/chipyard/src/main/scala/configs/RocketConfig.scala中创建了一个配置：
class JustReadTLRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithUART ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new my-chip.WithJustRead ++ // <=== THIS LINE ADDED
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)- 最后，我更改了主
build.sbt--在chipyard中的一个--以另外保存这些行：
lazy val my-chip = (project in file("generators/my-chip"))
.dependsOn(rocketchip, chisel_testers, midasTargetUtils)
.settings(commonSettings)和
lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
.dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
my-chip, // <=== ADDED THIS
dsptools, `rocket-dsptools`,
gemmini, icenet, tracegen, ariane, nvdla)
.settings(commonSettings)现在，当运行make CONFIG=JustReadTLRocketConfig时，我得到以下错误：
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
Picked up _JAVA_OPTIONS: -Xmx2048m
[info] Loading settings for project chipyard-build from plugins.sbt ...
[info] Loading project definition from /home/apaj/chipyard/project
[error] [/home/apaj/chipyard/build.sbt]:166: Pattern matching in val statements is not supported环顾四周并没有真正的帮助，因为我缺乏任何scala/软件构建技能，因此不能对这有太多的了解，例如.
我的蜘蛛感觉告诉我，我在芯片厂的内部组织中弄乱了一些东西，所以.请，一些有经验的用户的帮助将是非常感谢的。谢谢。
编辑:打印和添加第8点。
回答 1
Stack Overflow用户
回答已采纳
发布于 2022-03-03 16:36:06
错误来自于-中的lazy val my-chip和package my-chip。如果您想在scala名称中使用-，可以将该名称包装在后台，如`my-chip`。
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原文链接：
https://stackoverflow.com/questions/71237637
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