问访问std_logic_vectors的2D数组会产生意外的总线冲突。

EN

-- load configuration file (Generics and data type declaration )
use work.config_pkg.all;

entity systolic_array is
port (
    clk : in std_logic;
    rstn : in std_logic;

    -- "left side" inputs of the systolic array (arrays with size of number of rows, declared in conifguration-vhdl-file)
    xs : in input_vector_array;
    coeffs : in input_vector_array;
    ies : in input_vector_array;
    
    -- enable to declare then valid input data is provided
    en : in std_logic;
    
    -- output of systolic array (1D array of std_logic_vectors -> also declared in configuration file)
    ys : out row_exchange_array
);
end entity;

architecture behav of systolic_array is

    -- array to handle data from one row to the next
    -- JUST HERE FOR BETTER UNDERSTANDING, ACCTUALLY DECLARED IN CONFIGURATION FILE BECAUSE IT IS THE SAME TYPE AS THE OUTPUT "ys"
    type row_exchange_array is array (0 to ROW_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);

    -- 2D array to handle all exchanges in the systolic array (from row to row, ACCs and outputs)
    type exchange_array is array (0 to NUM_ROWS+1) of row_exchange_array;
    signal row_exchange : exchange_array;

begin

    -- first row gets all ys set to 0 as input
    row_exchange(0) <= (others => (others => '0'));
    -- last row is connected to output
    -- THIS IS THE THE PROBLEM SEEMS TO OCCUR
    ys <= row_exchange(NUM_ROWS+1);

    -- generation of the rows
    gen_rows : for j in 0 to NUM_ROWS-1 generate

        inst_row: systolic_row
        port map (
            clk   => clk,              -- clock
            i     => ies(j),           -- "left side" input to systolic array row
            coef  => coeffs(j),        -- "left side" input to systolic array row
            x     => xs(j),            -- "left side" input to systolic array row
            y_in  => row_exchange(j),  -- "top" input to systolic array row
            y_out => row_exchange(j+1) -- "bottom" output of systolic array row
        );

    end generate gen_rows;

    -- generation of the accumulators as the last row of the systolic array
    gen_accs : for j in 0 to ROW_WIDTH-1 generate

        inst_acc: ACC
        port map (
            clk => clk,                        -- clock
            rstn => rstn,                      -- reset (low active)
            en => en_shift_regs(NUM_ROWS+j),   -- enable for the accumulator (signal declaration not shown here, because not part of the problem, I guess)
            T   => row_exchange(NUM_ROWS)(j),  -- input (std_logic_vector)
            y   => row_exchange(NUM_ROWS+1)(j) -- ouput (std_logic_vector)
        );
    
    end generate gen_accs;

end architecture;