问使用测试台模拟VHDL计数器输出“未初始化”，这是如何解决的？

EN

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;

entity Lab_3_Source_File is
 generic(N_BITS : integer := 8);
 port(
 btnd : in STD_LOGIC ;
 clk : in STD_LOGIC;
 led : out STD_LOGIC_VECTOR(7 downto 0)
 );
end Lab_3_Source_File;

architecture counter of Lab_3_Source_File is
signal count: STD_LOGIC_VECTOR(7 downto 0);

begin

process(clk, btnd)
begin
 if btnd = '1' then
 count <= (others => '0');
 elsif rising_edge(clk) then
 count <= count + 1;
 end if;
end process;

 led <= count;
end counter;

use IEEE.STD_LOGIC_1164.ALL;


entity Count_TestBench is

end Count_TestBench;

architecture Behavioral of Count_TestBench is                               
                   
    signal btnd, clk : STD_LOGIC;
    signal led : STD_LOGIC_VECTOR(7 downto 0);
begin


   UUT : entity work.Lab_3_Source_File port map (btnd => btnd,clk => clk,led => led);
 
    process
    begin
        btnd<='1';
        wait for 1 ns;
        btnd<='0';    
        led<= (others => '0');           
        for i in 1 to 100 loop
            clk<='1';
            wait for 10 ns;
            clk<='0';
            wait for 10 ns;
            led<=led;
        end loop;          
    end process;
end Behavioral;