值部分传播到中间信号。
值部分传播到中间信号。
提问于 2020-06-23 11:59:42
我有一个名为入站的实体，它包括另一个名为entity_A的实体和一个用于入站的testbench tb。
我在tb中对entity_A的输出有一个别名，这样我就可以访问它，如下所示：
ALIAS alias_entity_A_out IS
<<SIGNAL .tb.inbound_inst.entity_A_inst.entity_A_out : INBOUND_RECORD_TYPE>>; 我的问题是，用于在entity_A_out_inst入站中实例化entity_A的输出中间信号(输出中间信号)正在获取entity_A_out输出端口的部分值，只有两位被分配，其余的未初始化，如下所示：
-- Instantiate entity_A
entity_A_inst : ENTITY work.entity_A(rtl)
PORT MAP(
clk => clk,
reset => reset,
entity_A_in => entity_A_in_inst,
entity_A_out => entity_A_out_inst); -- here only part of the values are propogated
# ** Note: rx_data in entity_A_out output port = 00000000
# ** Note: rx_data in entity_A_out_inst intermediate signal = 00UUUUUU
# ** Note: alias_rx_data = 00000000
# ** Note: rx_data in entity_A_out output port = 00000001
# ** Note: rx_data in entity_A_out_inst intermediate signal = 00UUUUUU
# ** Note: alias_rx_data = 00000001下面是我的入站代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
PACKAGE inbound_pkg IS
TYPE RX_PORT_RECORD IS RECORD
rx_data : UNSIGNED(7 DOWNTO 0);
valid : STD_LOGIC;
END RECORD RX_PORT_RECORD;
TYPE INBOUND_RECORD_TYPE IS RECORD
rx_port : RX_PORT_RECORD;
END RECORD INBOUND_RECORD_TYPE;
END PACKAGE inbound_pkg;
-----------------------------------------------------------
-----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.inbound_pkg.ALL;
ENTITY entity_A IS
PORT(clk : IN STD_LOGIC; -- Main clock
reset : IN STD_LOGIC; -- reset, active
entity_A_in : IN INBOUND_RECORD_TYPE;
entity_A_out : OUT INBOUND_RECORD_TYPE);
END ENTITY entity_A;
ARCHITECTURE rtl OF entity_A IS
BEGIN
seq_proc: PROCESS (clk, reset)
BEGIN -- for seq_proc
IF (reset = '1') THEN
entity_A_out.rx_port.rx_data <= (OTHERS => '0');
entity_A_out.rx_port.valid <= '0';
ELSIF rising_edge(clk) THEN
entity_A_out <= entity_A_in;
END IF;
END PROCESS seq_proc;
END ARCHITECTURE;
-----------------------------------------------------------
-----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.inbound_pkg.ALL;
ENTITY inbound IS
PORT(clk : IN STD_LOGIC; -- Main clock
reset : IN STD_LOGIC; -- reset, active
inbound_in : IN INBOUND_RECORD_TYPE;
inbound_out : OUT INBOUND_RECORD_TYPE);
END ENTITY inbound;
ARCHITECTURE rtl OF inbound IS
-- INTERNAL SIGNALS DECLARATION --
SIGNAL entity_A_in_inst : INBOUND_RECORD_TYPE;
SIGNAL entity_A_out_inst : INBOUND_RECORD_TYPE; -- this is the signal that is not working
BEGIN -- start of architecture --
-- for entity_A_in
entity_A_in_inst.rx_port <= inbound_in.rx_port;
-- for entity_A_out
inbound_out.rx_port <= entity_A_out_inst.rx_port;
-- Instantiate entity_A
entity_A_inst : ENTITY work.entity_A(rtl)
PORT MAP(
clk => clk,
reset => reset,
entity_A_in => entity_A_in_inst,
entity_A_out => entity_A_out_inst
);
END ARCHITECTURE;这是我的tb代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.inbound_pkg.ALL;
ENTITY tb IS
END ENTITY tb;
ARCHITECTURE sim OF tb IS
SIGNAL clk : STD_LOGIC := '0';
SIGNAL reset : STD_LOGIC := '1';
SIGNAL inbound_in_inst : INBOUND_RECORD_TYPE := (rx_port => ((others => '0'), '0'));
SIGNAL inbound_out_inst : INBOUND_RECORD_TYPE;
ALIAS alias_entity_A_out IS
<<SIGNAL .tb.inbound_inst.entity_A_inst.entity_A_out : INBOUND_RECORD_TYPE>>;
BEGIN -- start of architecture --
inbound_inst : ENTITY work.inbound(rtl)
PORT MAP(
clk => clk,
reset => reset,
inbound_in => inbound_in_inst,
inbound_out => inbound_out_inst);
clk <= NOT clk after 10 ns;
reset <= '0' after 30 ns;
test : PROCESS
begin
WAIT UNTIL reset = '0';
inbound_in_inst.rx_port.valid <= '0';
inbound_in_inst.rx_port.rx_data <= x"01";
WAIT UNTIL rising_edge(clk);
report "rx_data in entity_A_out output port = " & to_string(alias_entity_A_out.rx_port.rx_data);
report "rx_data in entity_A_out_inst intermediat signal = " & to_string(<<SIGNAL .tb.inbound_inst.entity_A_out_inst : INBOUND_RECORD_TYPE>>.rx_port.rx_data);
report "alias_rx_data = " & to_string(alias_entity_A_out.rx_port.rx_data);
inbound_in_inst.rx_port.rx_data <= x"02";
WAIT UNTIL rising_edge(clk);
report "rx_data in entity_A_out output port = " & to_string(alias_entity_A_out.rx_port.rx_data);
report "rx_data in entity_A_out_inst intermediat signal = " & to_string(<<SIGNAL .tb.inbound_inst.entity_A_out_inst : INBOUND_RECORD_TYPE>>.rx_port.rx_data);
report "alias_rx_data = " & to_string(alias_entity_A_out.rx_port.rx_data);
WAIT UNTIL rising_edge(clk);
wait for 100 ns;
END PROCESS test;
END ARCHITECTURE sim;我不明白这里的问题是什么，但是当我不使用Alias并在tb中声明entity_A_out信号并使用外部名称为其分配时，它工作得很好，如下所示：
SIGNAL entity_A_out: INBOUND_RECORD_TYPE;
entity_A_out <= <<SIGNAL .tb.inbound_inst.entity_A_inst.entity_A_out : INBOUND_RECORD_TYPE>>; 在这里你可以在EDA上看到它
回答 1
Stack Overflow用户
回答已采纳
发布于 2020-06-24 05:27:32
您的代码看起来是有效的，所以这一定是一个带有模拟器的bug。如果您切换到Riviera在EDA游乐场，它的工作，如预期。
页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/62534195
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