我创建了一个基本模块,用于表示Chisel3中的一个内存单元:
class MemristorCellBundle() extends Bundle {
val writeBus = Input(UInt(1.W))
val dataBus = Input(UInt(8.W))
val cellBus = Output(UInt(8.W))
}
class MemCell() extends Module {
val io = IO(new MemCellBundle())
val write = Wire(UInt())
write := io.voltageBus
val internalValue = Reg(UInt())
// More than 50% of total voltage in (255).
when(write === 1.U) {
internalValue := io.dataBus
io.cellBus := io.dataBus
} .otherwise {
io.cellBus := internalValue
}
}我想要的是,当internalValue总线逻辑较低时,它输出write,然后用逻辑高来改变这个值。我对Chisel的理解是,寄存器可以在时钟周期之间持久化这个internalValue,因此这基本上是一个内存单元。
我是这样做的,作为一个更大项目的一部分。然而,在编写单元测试时,我发现“读后写”方案失败了。
class MemCellTest extends FlatSpec with ChiselScalatestTester with Matchers {
behavior of "MemCell"
it should "read and write" in {
test(new MemCell()) { c =>
c.io.dataBus.poke(5.U)
c.io.write.poke(0.U)
c.io.cellBus.expect(0.U)
// Write
c.io.dataBus.poke(5.U)
c.io.write.poke(1.U)
c.io.cellBus.expect(5.U)
// Verify read-after-write
c.io.dataBus.poke(12.U)
c.io.write.poke(0.U)
c.io.cellBus.expect(5.U)
}
}
}前两个期望值和我预期的一样。但是,当我试图在写完后阅读时,cellBus返回到0,而不是持久化我以前编写的5。
test MemCell Success: 0 tests passed in 1 cycles in 0.035654 seconds 28.05 Hz
[info] MemCellTest:
[info] MemCell
[info] - should read and write *** FAILED ***
[info] io_cellBus=0 (0x0) did not equal expected=5 (0x5) (lines in MyTest.scala: 10) (MyTest.scala:21)显然,寄存器没有保留这个值,因此internalValue恢复为0。但为什么会发生这种情况,我如何才能创造一种能够持续存在的价值呢?
发布于 2021-12-02 04:17:38
Drakinite的评论是正确的。您需要确保对时钟进行分步,以便看到寄存器锁存值。我对您的测试进行了调整,使其包含了几个步骤,并如预期的那样工作:
c.io.dataBus.poke(5.U)
c.io.writeBus.poke(0.U)
c.io.cellBus.expect(0.U)
c.clock.step() // Added step
// Write passthrough (same cycle)
c.io.dataBus.poke(5.U)
c.io.writeBus.poke(1.U)
c.io.cellBus.expect(5.U)
c.clock.step() // Added step
// Verify read-after-write
c.io.dataBus.poke(12.U)
c.io.writeBus.poke(0.U)
c.io.cellBus.expect(5.U)下面是一个可执行的示例,说明这是可行的(使用chisel3 v3.4.4和chiseltest v0.3.4):https://scastie.scala-lang.org/5E1rOEsYSzSUrLXZCvoyNA
https://stackoverflow.com/questions/70193723
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