问如何在Verilog中连接两个模块？

EN

module dff (
    input Clk,
    input D,
    output Q,
    output Qbar
  );

  wire q_to_s;
  wire qbar_to_r;
  wire clk_bar;

  assign clk_bar = ~Clk;

  D_latch dlatch (
    .D(D),
    .Clk(Clk),
    .Q(q_to_s),
    .Qbar(qbar_to_r)
  );

  RS_latch rslatch (
    .S(q_to_s),
    .R(qbar_to_r),
    .Clk(clk_bar),
    .Qa(Q),
    .Qb(Qbar)
  );

endmodule