blocks|key|20496|text|这里有大量的缓存模拟器，例如，用于迪涅罗+(双关语显然是有意的)应该相当简单，并且经常用于教育目的。|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|20497|请注意，这个模拟器是跟踪驱动的，这意味着它提供了一个内存访问地址列表，它不知道如何运行二进制文件。您可以通过使用二进制工具来模拟这些跟踪。|style|BOLD|20498|http://software.intel.com/en-us/articles/pintool|unordered-list-item|20499|http://wiki.qemu.org/Main_Page|20500|http://bochs.sourceforge.net/|20501|等等。请注意，其中一些已经提供了内部缓存模拟器，可能还可以使用。|20502|其他模拟器可以模拟完整的CPU/系统行为，而不仅仅是缓存，因此可以支持运行二进制文件。其中大多数都包括一个模拟的缓存系统。例如：|20503|http://gem5.org/Main_Page|20504|http://www.simplescalar.com/|20505|http://www.multi2sim.org/|20506|http://marss86.org/~marss86/index.php/Home|20507|和其他许多人|20508|另一方面，编写自己的缓存模拟器相当简单--如果您可以处理内存跟踪(编写实际的前端要复杂得多)。您将无法获得关于Intel/AMD产品中实际缓存的过于详细的规范，但是基本功能在任何计算机体系结构教科书甚至wikipedia中都有详细说明，参数(大小、相关性、一致性策略)主要记录在已出版的指南中，并且可能在产品代际之间经常发生变化。如果遇到任何特定的问题，您总是可以在这里问:)|20509|编辑：|20510|关于问题的第二部分--没有关于英特尔CPU的确切缓存实现的公开文档，但是“规范”(大小、关联性、策略)在优化指南中：|20511|📷|atomic|20512|现在，对这些缓存进行建模应该是简单的，但是可能会有一些隐藏的警告，比如关机特性或专门的LRU行为。在这里可以找到这样一个报告的例子-+http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/+(如果是这样的话，它可能是值得实现的准确性)，但除此之外，我认为总体行为不应该受到这些细节的太大影响，为任何实际用途。|20513|entityMap|0|LINK|mutability|MUTABLE|url|http://pages.cs.wisc.edu/~markhill/DineroIV/|1|2|3|4|5|6|7|8|http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf|9|IMAGE|IMMUTABLE|imageUrl|https://developer.qcloudimg.com/http-save/yehe-900000/6f3852a49ab7ccbf07cc568e67dc1f09.jpg|imageAlt|10|http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/^0|H|3|0|0|A|5|0|0|1C|1|0|0|U|2|0|0|T|3|0|0|0|0|P|4|0|0|S|5|0|0|P|6|0|0|16|7|0|0|0|0|1G|4|8|0|0|1|9|0|1V|1L|A|0^^$0|@$1|2|3|4|5|6|7|22|8|@]|9|@$A|23|B|24|1|25]]|C|$]]|$1|D|3|E|5|6|7|26|8|@$A|27|B|28|F|G]]|9|@]|C|$]]|$1|H|3|I|5|J|7|29|8|@]|9|@$A|2A|B|2B|1|2C]]|C|$]]|$1|K|3|L|5|J|7|2D|8|@]|9|@$A|2E|B|2F|1|2G]]|C|$]]|$1|M|3|N|5|J|7|2H|8|@]|9|@$A|2I|B|2J|1|2K]]|C|$]]|$1|O|3|P|5|6|7|2L|8|@]|9|@]|C|$]]|$1|Q|3|R|5|6|7|2M|8|@]|9|@]|C|$]]|$1|S|3|T|5|J|7|2N|8|@]|9|@$A|2O|B|2P|1|2Q]]|C|$]]|$1|U|3|V|5|J|7|2R|8|@]|9|@$A|2S|B|2T|1|2U]]|C|$]]|$1|W|3|X|5|J|7|2V|8|@]|9|@$A|2W|B|2X|1|2Y]]|C|$]]|$1|Y|3|Z|5|J|7|2Z|8|@]|9|@$A|30|B|31|1|32]]|C|$]]|$1|10|3|11|5|6|7|33|8|@]|9|@]|C|$]]|$1|12|3|13|5|6|7|34|8|@]|9|@]|C|$]]|$1|14|3|15|5|6|7|35|8|@]|9|@]|C|$]]|$1|16|3|17|5|6|7|36|8|@]|9|@$A|37|B|38|1|39]]|C|$]]|$1|18|3|19|5|1A|7|3A|8|@]|9|@$A|3B|B|3C|1|3D]]|C|$]]|$1|1B|3|1C|5|6|7|3E|8|@]|9|@$A|3F|B|3G|1|3H]]|C|$]]|$1|1D|3|-4|5|6|7|3I|8|@]|9|@]|C|$]]]|1E|$1F|$5|1G|1H|1I|C|$1J|1K]]|1L|$5|1G|1H|1I|C|$1J|I]]|1M|$5|1G|1H|1I|C|$1J|L]]|1N|$5|1G|1H|1I|C|$1J|N]]|1O|$5|1G|1H|1I|C|$1J|T]]|1P|$5|1G|1H|1I|C|$1J|V]]|1Q|$5|1G|1H|1I|C|$1J|X]]|1R|$5|1G|1H|1I|C|$1J|Z]]|1S|$5|1G|1H|1I|C|$1J|1T]]|1U|$5|1V|1H|1W|C|$1X|1Y|1Z|-4]]|20|$5|1G|1H|1I|C|$1J|21]]]]

There are plenty of cache simulators out there, <a href="http://pages.cs.wisc.edu/~markhill/DineroIV/" rel="nofollow noreferrer">Dinero</a> for e.g. (pun obviously intended) should be fairly simple and is often used for educational purposes. 
Note that this simulator is trace-driven, it means it feeds on a list of memory access addresses, it doesn't know how to run a binary. You can produce such traces by emulating them with binary instrumentation tools, for e.g. 

<ul>
<li><a href="http://software.intel.com/en-us/articles/pintool" rel="nofollow noreferrer">pin</a></li>
<li><a href="http://wiki.qemu.org/Main_Page" rel="nofollow noreferrer">qemu</a></li>
<li><a href="http://bochs.sourceforge.net/" rel="nofollow noreferrer">bochs</a></li>
</ul>

etc.. Note that some of these offer internal cache simulators already, and may be possible to play with.

Other simulators can simulate full CPU/system behavior, not just caches, and can therefore support running a binary. Most of them include within them a simulated cache system. For e.g.:

<ul>
<li><a href="http://gem5.org/Main_Page" rel="nofollow noreferrer">gem5</a></li>
<li><a href="http://www.simplescalar.com/" rel="nofollow noreferrer">simplescalar</a></li>
<li><a href="http://www.multi2sim.org/" rel="nofollow noreferrer">multi2sim</a></li>
<li><a href="http://marss86.org/~marss86/index.php/Home" rel="nofollow noreferrer">marss86</a></li>
</ul>

and many others

On the other hand, writing your own cache simulator is fairly simple - if you can work on a memory trace (writing an actual fronend is way more complicated). You won't be able to get a too detailed spec on actual caches in Intel/AMD products, but the basic functionality is detailed in any computer architecture textbook or even wikipedia, the parameters (size, associativity, coherency policies) are mostly documented in the published guides, and may often change between product generations. You can always ask here if you encounter any specific question :)

<h1>Edit:</h1>

Regarding the second part of the question - there's no publicly available documentation of the exact cache implementation of Intel CPUs, but the dry "specs" (size, associativity, policies) are in the <a href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf" rel="nofollow noreferrer">optimization guide</a>:
<img src="https://i.stack.imgur.com/0EVZf.jpg" alt="Haswell caches">
Now, modeling these caches should be straightforward, but there may be some hidden caveats, like powerdown features or specialized LRU behaviors. One such reported example can be found here - <a href="http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/" rel="nofollow noreferrer">http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/</a> (if this is true, it might be worth implementing for accuracy), but aside from that I believe the overall behavior shouldn't be affected by these details too much, for any practical use.

I would like to model the behavior of caches in Intel architectures (LRU, inclusive, K-Way Associative, etc)., I've read wikipedia, Ulrich Drepper's great paper on memory, and the Intel Manual Volume 3A: System Programming Guide (chapter 11, but it's not very helpful, because they only explain what can be manipulated at the software level). I've also read a bunch of academic papers, but as usual, they do not make their code available for replication... even after asking for it. My question is, is there already a publicly available framework to model cache behavior? If not, is there a document detailing the behavior of caches from Intel at the deepest levels? I could not find one.

Implementing a cache modeling framework

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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