用Case语句实现JK触发器的VHDL程序
用Case语句实现JK触发器的VHDL程序
提问于 2018-09-09 00:07:30
library ieee;
use ieee. std_logic_1164.all;
entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin
process(clock,j,r)
begin
jk <= j & k;
if(clock= '1' and clock'event) then
case (jk) is
when "00" => temp<= temp;
when "01" => temp <= '0';
when "10" => temp <= '1';
when "11" => not temp;
when others => temp <= 'X'
end case;
end process;
q <= temp;
qbar <= not temp;
end behavioral;当我使用ghdl编译这个程序时，它显示错误' When‘而不是'not’。请帮我找出这个代码的问题。
回答 1
Stack Overflow用户
发布于 2018-09-09 21:22:23
你忘记了这些事情：
1)when "11" => not temp;到when "11" => temp <= not temp;
2) when others => temp <='X';末尾必须有分号when others => temp <= 'X'
3)在if的末尾，您错过了end if
4)过程敏感度列表包含一个未声明的名为‘r’的信号
我省略了进程中的信号j和k，因为您在if语句中执行的所有代码都是由时钟调节的，所以当j和k改变它们的值并且时钟不在上升沿时，就不需要执行进程了。
library ieee;
use ieee. std_logic_1164.all;
entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin
process(clock)
begin
jk <= j & k;
if(clock= '1' and clock'event) then
case (jk) is
when "00" => temp<= temp;
when "01" => temp <= '0';
when "10" => temp <= '1';
when "11" => temp <= not temp;
when others => temp <= 'X';
end case;
end if;
end process;
q <= temp;
qbar <= not temp;
end behavioral;页面原文内容由Stack Overflow提供。腾讯云小微IT领域专用引擎提供翻译支持
原文链接：
https://stackoverflow.com/questions/52237033
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