SystemVerilog接口多路复用器
SystemVerilog接口多路复用器
提问于 2016-08-19 18:28:01
我是systemverilog的新手，正在尝试构建一个systemverilog测试平台。我有一个DUT，它应该通过多路复用器连接到两个外部模块之一。我想在模拟过程中切换连接，我想使用systemverilog接口连接DUT和多路复用器以及多路复用器和两个外部模块之间的连接。接口中的信号是双向的。
我在写多路复用器时遇到了麻烦。我在当前的实现中得到了一个错误，即表达式的LHS不能是一条线。如果我将接口中的类型更改为逻辑，我会得到一个错误，指出这对于双向信号是不可能的。我尝试谷歌，但我没有找到任何关于连接接口到接口的教程。这是不可能的吗？或者有没有更好的方法来做我想做的事情？
到目前为止，我有以下几点：
interface flash_connect_interface;
wire interface_f_cle;
wire interface_f_ale;
endinterface: flash_connect_interface
module flash_connect_testbench_top;
[...]
// Interfaces
flash_connect_interface flash_connect_interface_i0();
flash_connect_interface flash_connect_interface_i1();
flash_connect_interface flash_connect_interface_i2();
// Connecting DUT to interface
flash_connect flash_connect_i0(
.flash_connect_interface_i(flash_connect_interface_i0),
);
// Multiplexer
flash_connect_mux mux1(
.flash_connect_interface_i_0(flash_connect_interface_i0),
.flash_connect_interface_i_1(flash_connect_interface_i1),
.flash_connect_interface_i_2(flash_connect_interface_i2),
.select(sel)
);
nand_model nand_model0 (
.Cle (flash_connect_interface_i1.interface_f_cle),
.Ale (flash_connect_interface_i1.interface_f_ale),
);
nand_model nand_model1 (
.Cle (flash_connect_interface_i2.interface_f_cle),
.Ale (flash_connect_interface_i2.interface_f_ale),
);
[...]
endmodule // end testbench_top
module flash_connect_mux(
flash_connect_interface flash_connect_interface_i_0,
flash_connect_interface flash_connect_interface_i_1,
flash_connect_interface flash_connect_interface_i_2,
input select
);
always_comb begin
// *** Here is the problem ***
if (select == 1'b0) flash_connect_interface_i_1 = flash_connect_interface_i_0;
else flash_connect_interface_i_2 = flash_connect_interface_i_0;
end
endmodule回答 1
Stack Overflow用户
发布于 2016-08-20 02:25:38
本例中的接口只是一堆电线。您的代码似乎没有任何明显的错误。但是，如果您试图根据select信号将接口直接分配给彼此，这将不起作用。您将需要根据选择信号分别指定所有焊线。多路复用接口没有什么特别之处。
下面的代码执行多路复用。
interface flash_connect_interface;
wire interface_f_cle;
wire interface_f_ale;
endinterface: flash_connect_interface
module nand_model ( inout Cle , inout Ale ) ; // Sample nand model
reg r = 1;
assign Cle = r?1:1'bz;
assign Ale = r?1:1'bz;
endmodule
module flash_connect_mux ( flash_connect_interface flash_connect_interface_i_0 , flash_connect_interface flash_connect_interface_i_1 , flash_connect_interface
flash_connect_interface_i_2 ,input [3:0] select ) ;
// Interconnect interface assignment
assign flash_connect_interface_i_0.interface_f_cle = (select== 0) ? flash_connect_interface_i_1.interface_f_cle : flash_connect_interface_i_2.interface_f_cle;
assign flash_connect_interface_i_0.interface_f_ale = (select== 0) ? flash_connect_interface_i_1.interface_f_ale : flash_connect_interface_i_2.interface_f_ale;
endmodule
module flash_connect ( flash_connect_interface flash_connect_interface_i ) ;
//check flash_connect_interface_i.interface_f_cle ;
//check flash_connect_interface_i.interface_f_ale ;
endmodule
module flash_connect_testbench_top;
reg [3:0] select ;
// Interfaces
flash_connect_interface flash_connect_interface_i0();
flash_connect_interface flash_connect_interface_i1();
flash_connect_interface flash_connect_interface_i2();
// Connecting DUT to interface
flash_connect flash_connect_i0(
.flash_connect_interface_i(flash_connect_interface_i0)
);
// Multiplexer
flash_connect_mux mux1(
.flash_connect_interface_i_0(flash_connect_interface_i0),
.flash_connect_interface_i_1(flash_connect_interface_i1),
.flash_connect_interface_i_2(flash_connect_interface_i2),
.select(select)
);
nand_model nand_model0 (
.Cle (flash_connect_interface_i1.interface_f_cle),
.Ale (flash_connect_interface_i1.interface_f_ale)
);
nand_model nand_model1 (
.Cle (flash_connect_interface_i2.interface_f_cle),
.Ale (flash_connect_interface_i2.interface_f_ale)
);
endmodule // end testbench_top链接到界面教程- https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/
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原文链接：
https://stackoverflow.com/questions/39036710
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