问如何删除chisel3顶层模块的时钟信号？

EN

class Top extends Module {
  val io = IO(new Bundle{
    val clock_p = Input(Clock())
    val clock_n = Input(Clock())
    val led = Output(Bool())
  })

  val ibufds = Module(new IBUFDS)
  ibufds.io.I := io.clock_p
  ibufds.io.IB:= io.clock_n

  val blink = Module(new Blink)
  blink.clock := ibufds.io.O
  io.led := blink.io.led  

}

module Top(
  input   clock,
  input   reset,
  input   io_clock_p,
  input   io_clock_n,
  output  io_led
);
...