blocks|key|4447826|text|简单的回答是:不！|type|unstyled|depth|inlineStyleRanges|entityRanges|data|4447827|更详细地说，SSE寄存器是128位宽的，但不存在将它们视为128位整数的指令。充其量，这些寄存器被视为两个64位(无符号)整数。像加法/...这样的操作可以通过将这两个64位值并行相加并手动处理溢出来构造，但不能使用单个指令。实现这一点可能会变得非常复杂和“丑陋”，看这里：|4447828|How+can+I+add+together+two+SSE+registers|offset|length|4447829|这将不得不为每个基本操作完成，与使用64位通用寄存器(软件中的“仿真”)实现相比，这些操作可能具有可疑的优势。另一方面，这种SSE方法的一个优点是，一旦它被实现，它也将工作于256位整数(AVX2)和512位整数(AVX512)，只需进行较小的修改。|4447830|entityMap|0|LINK|mutability|MUTABLE|url|https://stackoverflow.com/q/24161243/1305969^0|0|0|0|14|0|0|0^^$0|@$1|2|3|4|5|6|7|R|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|S|8|@]|9|@]|A|$]]|$1|D|3|E|5|6|7|T|8|@]|9|@$F|U|G|V|1|W]]|A|$]]|$1|H|3|I|5|6|7|X|8|@]|9|@]|A|$]]|$1|J|3|-4|5|6|7|Y|8|@]|9|@]|A|$]]]|K|$L|$5|M|N|O|A|$P|Q]]]]

Short answer is: NO!

To elaborate more, the SSE registers are 128-bit wide, but no instructions exist to treat them as 128-bit-integers. At best, these registers are treated as two 64-bit (un)signed integers. Operations like addition/... can be constructed by parallely adding these two 64-bit-values and manually handling overflow, but not with a single instruction. Implementing this can get quite complicated and "ugly", look here:

<a href="https://stackoverflow.com/q/24161243/1305969">How can I add together two SSE registers</a>

This would have to be done for every basic operation with probably questionable advantages compared to an implemention with 64-bit general purpose registers ("emulation" in software). On the other hand, an advantage of this SSE-approach would be that once it is implemented, it will also work for 256-bit-integers(AVX2) and 512-bit-integers(AVX-512) with only minor modifications.

blocks|key|4447986|text|x86-64指令集可以使用一条指令执行64位*64位到128位(无符号imul为mul，有符号imul为每个有一个操作数)，因此我认为在某种程度上，x86指令集确实包括对128位整数的一些支持。|type|unstyled|depth|inlineStyleRanges|offset|length|style|CODE|entityRanges|data|4447987|如果您的指令集没有执行64位*64位到128位的指令，那么您需要several+instructions+to+emulate+this。|4447988|这就是为什么使用x86-64只需很少的指令就可以完成128位*128位到低128位的操作的原因。举个例子，和GCC|4447989|__int128+mul(__int128+a,+__int128+b)+{
++++return+a*b;
}|code-block|syntax|javascript|4447990|生成此程序集|4447991|imulq+++%25rdx,+%25rsi
movq++++%25rdi,+%25rax
imulq+++%25rdi,+%25rcx
mulq++++%25rdx
addq++++%25rsi,+%25rcx
addq++++%25rcx,+%25rdx|4447992|它使用一个64位*64位到128位指令，两个64位*64位来降低64位指令，以及两个64位加法。|4447993|entityMap|0|LINK|mutability|MUTABLE|url|https://stackoverflow.com/questions/28807341/simd-signed-with-unsigned-multiplication-for-64-bit-64-bit-to-128-bit^0|Z|4|14|3|1B|4|0|W|10|0|0|0|0|0|0|0^^$0|@$1|2|3|4|5|6|7|12|8|@$9|13|A|14|B|C]|$9|15|A|16|B|C]|$9|17|A|18|B|C]]|D|@]|E|$]]|$1|F|3|G|5|6|7|19|8|@]|D|@$9|1A|A|1B|1|1C]]|E|$]]|$1|H|3|I|5|6|7|1D|8|@]|D|@]|E|$]]|$1|J|3|K|5|L|7|1E|8|@]|D|@]|E|$M|N]]|$1|O|3|P|5|6|7|1F|8|@]|D|@]|E|$]]|$1|Q|3|R|5|L|7|1G|8|@]|D|@]|E|$M|N]]|$1|S|3|T|5|6|7|1H|8|@]|D|@]|E|$]]|$1|U|3|-4|5|6|7|1I|8|@]|D|@]|E|$]]]|V|$W|$5|X|Y|Z|E|$10|11]]]]

The x86-64 instruction set can do 64-bit*64-bit to 128-bit using one instruction (<code>mul</code> for unsigned <code>imul</code> for signed each with one operand) so I would argue that to some degree that the x86 instruction set does include some support for 128-bit integers.

If your instruction set does not have an instruction to do 64-bit*64-bit to 128-bit then you need <a href="https://stackoverflow.com/questions/28807341/simd-signed-with-unsigned-multiplication-for-64-bit-64-bit-to-128-bit">several instructions to emulate this</a>.

This is why 128-bit * 128-bit to lower 128-bit operations can be done with few instructions with x86-64. For example with GCC

<pre><code>__int128 mul(__int128 a, __int128 b) {
 return a*b;
}
</code></pre>

produces this assembly 

<pre><code>imulq %rdx, %rsi
movq %rdi, %rax
imulq %rdi, %rcx
mulq %rdx
addq %rsi, %rcx
addq %rcx, %rdx
</code></pre>

which uses one 64-bit * 64-bit to 128-bit instructions, two 64-bit * 64-bit to lower 64-bit instructions, and two 64-bit additions.

blocks|key|4447918|text|RISC-V有一个128b的候选ISA，RV128I。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|4447919|https://github.com/brucehoult/riscv-meta/blob/master/doc/src/rv128.md|offset|length|4447920|然而，在这一点上，它只是一个架构，它并没有被冻结。|4447921|entityMap|0|LINK|mutability|MUTABLE|url^0|0|0|1X|0|0|0^^$0|@$1|2|3|4|5|6|7|O|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|P|8|@]|9|@$D|Q|E|R|1|S]]|A|$]]|$1|F|3|G|5|6|7|T|8|@]|9|@]|A|$]]|$1|H|3|-4|5|6|7|U|8|@]|9|@]|A|$]]]|I|$J|$5|K|L|M|A|$N|C]]]]

RISC-V has a candidate ISA for 128b, RV128I.
<a href="https://github.com/brucehoult/riscv-meta/blob/master/doc/src/rv128.md" rel="nofollow noreferrer">https://github.com/brucehoult/riscv-meta/blob/master/doc/src/rv128.md</a>
However, at this point it is only an architecture and it isn't frozen.

Do we still need to emulate 128bit integers in software, or is there hardware support for them in your average desktop processor these days?

Is there hardware support for 128bit integers in modern processors?

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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我们是否仍然需要在软件中模拟128位整数，或者现在您的普通桌面处理器中是否有对它们的硬件支持？

问在现代处理器中是否有128位整数的硬件支持？
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问在现代处理器中是否有128位整数的硬件支持？EN