下面是我为XST用verilog编写的代码片段。日志中充满了错误。如何更正代码?如何以及在何处使用always@()和@()块?我在哪里使用阻塞和非阻塞赋值?
input wire CLOCK;
input wire [31:0] OUT_SQRT;
output wire [31:0] IN_SQRT;
input wire [31:0] RANDP;
integer randp;
integer flagp;
integer sqrootp;
integer check_primep;
always @(posedge CLOCK and flagp != 0)
begin
#10
@(posedge and flagp != 0 )
begin
flagp = sqrootp%check_primep;
if(flagp != 0 and check_primep < sqrootp)
begin
check_primep = check_primep + 1;
end
@(posedge and flagp == 0)
begin
flagp = 1;
check_primep = 2;
randp = RANDP;
#5
IN_SQRT = randp;
#10
sqrootp = OUT_SQRT;
end
endhttps://stackoverflow.com/questions/38180586
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