blocks|key|1819180|text|为您的代码提供Minimal,+Complete,+and+Verifiable+example：|type|unstyled|depth|inlineStyleRanges|entityRanges|offset|length|data|1819181|library+ieee;
use+ieee.std_logic_1164.all;
use+std.textio.all;

entity+main+is
++++port+(
++++++++rstb:+++++++in++std_logic;
++++++++clk:++++++++in++std_logic;
++++++++row:++++++++out+integer;
++++++++col:++++++++out+integer;
++++++++last_elem:++out+integer
++++);
end+entity+main;

architecture+behavioral+of+main+is
++++--+type+matrixdata+is+array+(0+to+240,+0+to+217)+of+integer;
++++type+matrixdata+is+array+(0+to+3,+0+to+2)+of+integer;
++++signal+data:++++matrixdata;
++++signal+test:++++integer;

begin
++++process+(clk)
++++++++file+read_file:+++++++++text;
++++++++variable+file_line:+++++line;
++++++++variable+row_counter:+++integer+:=+0;
++++++++variable+rows:++++++++++integer;
++++++++variable+cols:++++++++++integer;
++++++++variable+read_value:++++integer;
++++begin
++++++++--file_open(read_file,+"d:\faculta\an+3+sem+2\scs\image.txt",+read_mode);
++++++++file_open+(read_file,+"image.txt",+read_mode);
++++++++readline+(read_file,+file_line);
++++++++read+(file_line,+rows);
++++++++read+(file_line,+cols);
++++++++row+<=+rows;
++++++++col+<=+cols;

++++++++for+i+in+0+to+rows+-+1+loop
++++++++++++readline+(read_file,+file_line);
++++++++++++for+j+in+0+to+cols+-+1+loop
++++++++++++++++++++read(file_line,+read_value);
++++++++++++++++++++data(i,j)+<=+read_value;
++++++++++++end+loop;
++++++++end+loop;

++++++++test+<=+data(0,+0);
++++++++last_elem+<=+test;

++++++++file_close(read_file);
++++end+process;
end+behavioral;

library+ieee;
use+ieee.std_logic_1164.all;

entity+main_tb+is
end+entity;

architecture+foo+of+main_tb+is
++++component+main+is
++++++++port+(
++++++++++++rstb:+++++++in++std_logic;
++++++++++++clk:++++++++in++std_logic;
++++++++++++row:++++++++out+integer;
++++++++++++col:++++++++out+integer;
++++++++++++last_elem:++out+integer
++++++++);
++++end+component+main;
++++signal+rstb:+++++++std_logic+:=+'1';
++++signal+clk:++++++++std_logic+:=+'0';
++++signal+row:++++++++integer;
++++signal+col:++++++++integer;
++++signal+last_elem:++integer;
begin
DUT:
++++main
++++++++port+map+(
++++++++++++rstb+=>+rstb,
++++++++++++clk+=>+clk,
++++++++++++row+=>+row,
++++++++++++col+=>+col,
++++++++++++last_elem+=>+last_elem
++++++++);
WAVEFORM_DISPLAY_STIMULUS:
++++process
++++begin
++++++++wait+for+0+ns;
++++++++wait+for+1+ns;
++++++++wait;
++++end+process;
end+architecture;|code-block|syntax|javascript|1819182|针对较小的二维矩阵数据类型进行了修改，并随输入文件一起提供：|1819183|images.txt|1819184|4+3
0+0+0
1+1+1
2+2+2
3+3+3|1819185|我们看到：|1819186|​|1819187|📷|atomic|1819188|1819189|矩阵的值看起来是正确读入的。和test一样，last_elem信号也有缺省值(INTEGER‘’LOW，-2147483648)，这两个声明都缺少初始值。|style|CODE|1819190|Data和test都不在过程敏感度列表中，在调度分配的同一模拟周期中不会发生分配。每个进程至少执行一次。|1819191|进程敏感度列表还有一个问题。该过程将针对clk上的每个事件执行，重复打开文件、读取数据和关闭文件。|1819192|解决这两个问题的正确方法是删除进程敏感度列表，并在file_close后面添加最后一个等待语句(wait;)。此外，根据进程中先前的信号分配值，在每个信号分配之前添加一个具有零增量模拟时间(例如wait+for+0+ns;)的等待语句。|1819193|还存在纹理操作(file_open、read_line)期间的错误检测问题。你已经费了好大劲才关闭了这个文件。在执行procedure+read_line之前，如何检查文件是否成功打开和终止？|1819194|++++process
++++++++file+read_file:+++++++++text;
++++++++variable+file_line:+++++line;
++++++++variable+row_counter:+++integer+:=+0;
++++++++variable+rows:++++++++++integer;
++++++++variable+cols:++++++++++integer;
++++++++variable+read_value:++++integer;
++++++++variable+open_status:+++FILE_OPEN_STATUS;+--+ADDED
++++begin
++++++++--file_open(read_file,+"d:\faculta\an+3+sem+2\scs\image.txt",+read_mode);
++++++++--+file_open+(read_file,+"image.txt",+read_mode);
++++++++file_open+(open_status,+read_file,+"image.txt",+read_mode);

++++++++case+open_status+is++--+ADDED
+++++++++++++when+OPEN_OK+=>
++++++++++++++++report+"read_file+opened+for+read"+severity+NOTE;
++++++++++++when+STATUS_ERROR+=>
++++++++++++++++report+"read_file+already+open"+severity+FAILURE;
++++++++++++when+NAME_ERROR+=>
++++++++++++++++report+"read_file+file+name+not+found"+severity+FAILURE;
++++++++++++when+MODE_ERROR+=>
++++++++++++++++report+"read_file+can't+be+opened+for+read"+severity+FAILURE;
++++++++end+case;

++++++++if+endfile(read_file)+then++--+ADDED
++++++++++++report+"can't+read+first+line+from+read_file"
++++++++++++severity+FAILURE;
++++++++end+if;
++++++++readline+(read_file,+file_line);
++++++++read+(file_line,+rows);
++++++++read+(file_line,+cols);
++++++++row+<=+rows;
++++++++col+<=+cols;

++++++++for+i+in+0+to+rows+-+1+loop
++++++++++++if+endfile(read_file)+then+++--+ADDED
++++++++++++++++report+"can't+read+line+for+all+rows+from+read_file"
++++++++++++++++severity+FAILURE;
++++++++++++end+if;
++++++++++++readline+(read_file,+file_line);
++++++++++++for+j+in+0+to+cols+-+1+loop
++++++++++++++++++++read(file_line,+read_value);
++++++++++++++++++++data(i,j)+<=+read_value;
++++++++++++end+loop;
++++++++end+loop;
++++++++wait+for+0+ns;++--++ADDED+causes+a+delta+cycle,+data+is+updated
++++++++test+<=+data(0,+0);
++++++++wait+for+0+ns;++--+ADDED+causes+a+delta+cycle,+test+is+updated
++++++++last_elem+<=+test;
++++++++file_close(read_file);
++++++++wait;+++++++++++--+ADDED
++++end+process;|1819195|这将在初始化时加载阵列一次，并且last_elem值将在连续的增量模拟周期后更新。|1819196|wait语句会导致正在执行的进程挂起，直到满足条件为止。没有条件的wait语句假定超时子句为TIME‘’HIGH.|1819197|带有timeout子句的wait语句(这里的前两个是0+ns+)将暂停进程，直到满足条件为止。增量延迟等于当前模拟时间加上时间表达式。|1819198|由于为当前模拟时间安排了另一个事件，因此将发生增量模拟循环，在该循环中该过程将继续。在每个仿真周期开始时，为当前仿真时间调度的投影输出波形值导致信号更新，其中可以评估信号的有效值(如在赋值语句中)。前两个wait语句都会发生这种情况。|1819199|命中不带timeout子句的最后一个wait语句假设timeout子句为TIME‘’HIGH，则在模拟期间进程不会再次恢复。|1819200|您可以通过操作主机文件系统(路径和权限)和image.txt文件内容来证明open_status和endfile测试是有效的。|1819201|对测试工作台进行额外的更改：|1819202|CLOCK:
++++process
++++begin
++++++++wait+for+5+ns;
++++++++clk+<=+not+clk;
++++++++if+now+>+40+ns+then
++++++++++++wait;
++++++++end+if;
++++end+process;
--+WAVEFORM_DISPLAY_STIMULUS:
--+++++process
--+++++begin
--+++++++++wait+for+0+ns;
--+++++++++wait+for+1+ns;
--+++++++++wait;
--+++++end+process;|1819203|您可以通过模拟演示代码的功能：|1819204|1819205|1819206|1819207|在模拟时，您将只在第一行启动该过程一次，仅恢复两次等待信号更新，并且仅从|1819208|++++++++++++++++report+"read_file+opened+for+read"+severity+NOTE;+|1819209|在评估open_status时。|1819210|正如Tricky在评论中指出的那样，test被赋值为Data(0,+0)，然后赋值给last_element，实际上包含矩阵的第一个元素。|1819211|entityMap|0|LINK|mutability|MUTABLE|url|https://stackoverflow.com/help/mcve|1|IMAGE|IMMUTABLE|imageUrl|https://ask.qcloudimg.com/http-save/yehe-900000/6218d81de8b096acc34195381463debc.jpeg|imageAlt|2|https://ask.qcloudimg.com/http-save/yehe-900000/c26b011b57626e011cdfa385c8c4378f.jpeg^0|7|15|0|0|0|0|0|0|0|0|0|1|1|0|0|F|4|M|9|0|0|4|5|4|0|K|3|0|1C|5|2P|E|0|0|0|G|9|0|0|Q|4|0|0|0|11|B|1D|7|0|0|0|0|0|0|1|2|0|0|0|0|3|B|0|I|4|Q|A|16|C|0^^$0|@$1|2|3|4|5|6|7|2J|8|@]|9|@$A|2K|B|2L|1|2M]]|C|$]]|$1|D|3|E|5|F|7|2N|8|@]|9|@]|C|$G|H]]|$1|I|3|J|5|6|7|2O|8|@]|9|@]|C|$]]|$1|K|3|L|5|6|7|2P|8|@]|9|@]|C|$]]|$1|M|3|N|5|F|7|2Q|8|@]|9|@]|C|$G|H]]|$1|O|3|P|5|6|7|2R|8|@]|9|@]|C|$]]|$1|Q|3|R|5|6|7|2S|8|@]|9|@]|C|$]]|$1|S|3|T|5|U|7|2T|8|@]|9|@$A|2U|B|2V|1|2W]]|C|$]]|$1|V|3|R|5|6|7|2X|8|@]|9|@]|C|$]]|$1|W|3|X|5|6|7|2Y|8|@$A|2Z|B|30|Y|Z]|$A|31|B|32|Y|Z]]|9|@]|C|$]]|$1|10|3|11|5|6|7|33|8|@$A|34|B|35|Y|Z]|$A|36|B|37|Y|Z]]|9|@]|C|$]]|$1|12|3|13|5|6|7|38|8|@$A|39|B|3A|Y|Z]]|9|@]|C|$]]|$1|14|3|15|5|6|7|3B|8|@$A|3C|B|3D|Y|Z]|$A|3E|B|3F|Y|Z]]|9|@]|C|$]]|$1|16|3|17|5|6|7|3G|8|@]|9|@]|C|$]]|$1|18|3|19|5|F|7|3H|8|@]|9|@]|C|$G|H]]|$1|1A|3|1B|5|6|7|3I|8|@$A|3J|B|3K|Y|Z]]|9|@]|C|$]]|$1|1C|3|1D|5|6|7|3L|8|@]|9|@]|C|$]]|$1|1E|3|1F|5|6|7|3M|8|@$A|3N|B|3O|Y|Z]]|9|@]|C|$]]|$1|1G|3|1H|5|6|7|3P|8|@]|9|@]|C|$]]|$1|1I|3|1J|5|6|7|3Q|8|@]|9|@]|C|$]]|$1|1K|3|1L|5|6|7|3R|8|@$A|3S|B|3T|Y|Z]|$A|3U|B|3V|Y|Z]]|9|@]|C|$]]|$1|1M|3|1N|5|6|7|3W|8|@]|9|@]|C|$]]|$1|1O|3|1P|5|F|7|3X|8|@]|9|@]|C|$G|H]]|$1|1Q|3|1R|5|6|7|3Y|8|@]|9|@]|C|$]]|$1|1S|3|R|5|6|7|3Z|8|@]|9|@]|C|$]]|$1|1T|3|T|5|U|7|40|8|@]|9|@$A|41|B|42|1|43]]|C|$]]|$1|1U|3|R|5|6|7|44|8|@]|9|@]|C|$]]|$1|1V|3|1W|5|6|7|45|8|@]|9|@]|C|$]]|$1|1X|3|1Y|5|F|7|46|8|@]|9|@]|C|$G|H]]|$1|1Z|3|20|5|6|7|47|8|@$A|48|B|49|Y|Z]]|9|@]|C|$]]|$1|21|3|22|5|6|7|4A|8|@$A|4B|B|4C|Y|Z]|$A|4D|B|4E|Y|Z]|$A|4F|B|4G|Y|Z]]|9|@]|C|$]]|$1|23|3|-4|5|6|7|4H|8|@]|9|@]|C|$]]]|24|$25|$5|26|27|28|C|$29|2A]]|2B|$5|2C|27|2D|C|$2E|2F|2G|-4]]|2H|$5|2C|27|2D|C|$2E|2I|2G|-4]]]]

Providing a <a href="https://stackoverflow.com/help/mcve">Minimal, Complete, and Verifiable example</a> for your code:

<pre class="lang-vhdl prettyprint-override"><code>library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity main is
 port (
 rstb: in std_logic;
 clk: in std_logic;
 row: out integer;
 col: out integer;
 last_elem: out integer
 );
end entity main;

architecture behavioral of main is
 -- type matrixdata is array (0 to 240, 0 to 217) of integer;
 type matrixdata is array (0 to 3, 0 to 2) of integer;
 signal data: matrixdata;
 signal test: integer;

begin
 process (clk)
 file read_file: text;
 variable file_line: line;
 variable row_counter: integer := 0;
 variable rows: integer;
 variable cols: integer;
 variable read_value: integer;
 begin
 --file_open(read_file, "d:\faculta\an 3 sem 2\scs\image.txt", read_mode);
 file_open (read_file, "image.txt", read_mode);
 readline (read_file, file_line);
 read (file_line, rows);
 read (file_line, cols);
 row &lt;= rows;
 col &lt;= cols;

 for i in 0 to rows - 1 loop
 readline (read_file, file_line);
 for j in 0 to cols - 1 loop
 read(file_line, read_value);
 data(i,j) &lt;= read_value;
 end loop;
 end loop;

 test &lt;= data(0, 0);
 last_elem &lt;= test;

 file_close(read_file);
 end process;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity main_tb is
end entity;

architecture foo of main_tb is
 component main is
 port (
 rstb: in std_logic;
 clk: in std_logic;
 row: out integer;
 col: out integer;
 last_elem: out integer
 );
 end component main;
 signal rstb: std_logic := '1';
 signal clk: std_logic := '0';
 signal row: integer;
 signal col: integer;
 signal last_elem: integer;
begin
DUT:
 main
 port map (
 rstb =&gt; rstb,
 clk =&gt; clk,
 row =&gt; row,
 col =&gt; col,
 last_elem =&gt; last_elem
 );
WAVEFORM_DISPLAY_STIMULUS:
 process
 begin
 wait for 0 ns;
 wait for 1 ns;
 wait;
 end process;
end architecture;
</code></pre>

Modified for a smaller two dimensional matrixdata type and supplied with a an input file:

images.txt 

<pre class="lang-none prettyprint-override"><code>4 3
0 0 0
1 1 1
2 2 2
3 3 3
</code></pre>

We see:

<a href="https://i.stack.imgur.com/dM6Qt.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dM6Qt.jpg" alt="main_tb.jpg"></a>

Where the matrix values appear to be read in correctly. The <code>last_elem</code> signal has the default value (INTEGER'LOW, -2147483648) as does <code>test</code>, both declarations lacking an initial value.

Neither <code>Data</code> nor <code>test</code> are in the process sensitivity list assignments will not occur in the same simulation cycle an assignment is scheduled. Every process executes at least once.

There's also an issue with the process sensitivity list. The process will execute for each event on <code>clk</code>, repetitively opening the file, reading in data and closing the file.

The proper fix for these two issues would be to remove the process sensitivity list and add a final wait statement (<code>wait;</code>) after the file_close. Also add a wait statement with zero incremental simulation time (e.g. <code>wait for 0 ns;</code>) prior to each signal assignment depending on a previous signal assignment value in the process. 

There's also the issue of error detection during TEXTIO operations (file_open, read_line). You've gone to all the trouble to close the file. How about checking for a successful file open and ENDFILE before executing procedure read_line?

<pre class="lang-vhdl prettyprint-override"><code>
 process
 file read_file: text;
 variable file_line: line;
 variable row_counter: integer := 0;
 variable rows: integer;
 variable cols: integer;
 variable read_value: integer;
 variable open_status: FILE_OPEN_STATUS; -- ADDED
 begin
 --file_open(read_file, "d:\faculta\an 3 sem 2\scs\image.txt", read_mode);
 -- file_open (read_file, "image.txt", read_mode);
 file_open (open_status, read_file, "image.txt", read_mode);

 case open_status is -- ADDED
 when OPEN_OK =&gt;
 report "read_file opened for read" severity NOTE;
 when STATUS_ERROR =&gt;
 report "read_file already open" severity FAILURE;
 when NAME_ERROR =&gt;
 report "read_file file name not found" severity FAILURE;
 when MODE_ERROR =&gt;
 report "read_file can't be opened for read" severity FAILURE;
 end case;

 if endfile(read_file) then -- ADDED
 report "can't read first line from read_file"
 severity FAILURE;
 end if;
 readline (read_file, file_line);
 read (file_line, rows);
 read (file_line, cols);
 row &lt;= rows;
 col &lt;= cols;

 for i in 0 to rows - 1 loop
 if endfile(read_file) then -- ADDED
 report "can't read line for all rows from read_file"
 severity FAILURE;
 end if;
 readline (read_file, file_line);
 for j in 0 to cols - 1 loop
 read(file_line, read_value);
 data(i,j) &lt;= read_value;
 end loop;
 end loop;
 wait for 0 ns; -- ADDED causes a delta cycle, data is updated
 test &lt;= data(0, 0);
 wait for 0 ns; -- ADDED causes a delta cycle, test is updated
 last_elem &lt;= test;
 file_close(read_file);
 wait; -- ADDED
 end process;
</code></pre>

This loads the array once at initialization and <code>last_elem</code> value will be updated after successive delta simulation cycles. 

A wait statement causes an executing process to suspend until a condition is met. A wait statement without a condition assumes a timeout clause of TIME'HIGH. 

A wait statement with a timeout clause (here <code>0 ns</code> for the first two) will suspend the process until the condition is met. The incremental delay is equivalent to the current simulation time plus the time expression. 

Because there's a further event scheduled for the current simulation time, a delta simulation cycle will occur in which the process resumes. At the beginning of each simulation cycle projected output waveform values scheduled for the current simulation time cause signal updates where the effective value of the signal can be evaluated (as in an assignment statement). This will occur for both of the first two wait statements.

Hitting the final wait statement without a timeout clause assume a timeout clause of TIME'HIGH, the process won't resume again during simulation.

You can prove the <code>open_status</code> and <code>endfile</code> tests work by manipulating the host file system (path and permissions) and image.txt file contents. 

With an additional change to the testbench:

<pre class="lang-vhdl prettyprint-override"><code>CLOCK:
 process
 begin
 wait for 5 ns;
 clk &lt;= not clk;
 if now &gt; 40 ns then
 wait;
 end if;
 end process;
-- WAVEFORM_DISPLAY_STIMULUS:
-- process
-- begin
-- wait for 0 ns;
-- wait for 1 ns;
-- wait;
-- end process;
</code></pre>

You can demonstrate the code appears functional through simulation:

<a href="https://i.stack.imgur.com/vIMN0.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vIMN0.jpg" alt="main_tb_fixed.jpg"></a>

When simulating you'll only start the process at the first line once, only resume twice waiting on signal updates and only get one message from

<pre class="lang-vhdl prettyprint-override"><code> report "read_file opened for read" severity NOTE; 
</code></pre>

when evaluating <code>open_status</code>.

As Tricky points out in a comment <code>test</code> is assigned the value of <code>Data(0, 0)</code> which is then assigned to <code>last_element</code> and actually contains the first element of the matrix.

I am trying to read a matrix from a file, it contains the colors of the pixels of a gray scale image. After this I will have to put the data I read into a register and perform some operations on it. When I am trying to simulate my code, the data is read alright in the "data" signal, but when I try to store an element, I read in the "test" signal to show it in the "last_elem" output it shows -2147483648. What am I doing wrong and why can't I access the data I read? 

<pre><code>entity Main is
Port(
rstb:in std_logic;
clk:in std_logic;
row:out integer;
col:out integer;
last_elem:out integer
);
end Main;

architecture Behavioral of Main is
type matrixData is array(0 to 240, 0 to 217) of integer;
signal data:matrixData;
signal test:integer;

begin
 process(clk)
 file read_file:text;
 VARIABLE file_line:LINE;
 VARIABLE row_counter:INTEGER:=0;
 variable rows:integer;
 variable cols:integer;
 variable read_value:integer;
 begin


 file_open(read_file, "D:\Faculta\An 3 Sem 2\SCS\image.txt", read_mode);
 readline(read_file,file_line);
 read(file_line, rows);
 read(file_line, cols);
 row&lt;=rows;
 col&lt;=cols;

 for i in 0 to rows-1 loop
 readline(read_file,file_line);
 for j in 0 to cols-1 loop
 read(file_line, read_value);
 data(i,j)&lt;=read_value;
 end loop;
 end loop;



 test&lt;=data(0,0);
 last_elem&lt;=test;

 file_close(read_file);
 end process;

end Behavioral;
</code></pre>

Reading a matrix from file

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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我正在尝试从一个文件中读取一个矩阵，它包含一个灰度图像像素的颜色。在此之后，我必须将读取的数据放入一个寄存器中，并对其执行一些操作。当我试图模拟我的代码时，数据在" data“信号中可以正常读取，但当我试图存储一个元素时，我读取了"test”信号，并将其显示在"last_elem“输出中，它显示为-2147483648...

从文件中读取矩阵-腾讯云开发者社区-腾讯云

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