在Verilog FSM代码方面，状态转换是如何工作的？

module fsm (
  input wire clk,
  input wire reset,
  input wire input_signal,
  output wire output_signal
);

  // 定义状态
  typedef enum logic [1:0] {
    STATE_A,
    STATE_B,
    STATE_C
  } state_t;

  // 定义当前状态和下一个状态
  reg state_t current_state;
  reg state_t next_state;

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      current_state <= STATE_A; // 初始状态
    end else begin
      current_state <= next_state; // 更新当前状态
    end
  end

  always @(current_state or input_signal) begin
    case (current_state)
      STATE_A: begin
        // 根据输入信号决定下一个状态
        if (input_signal) begin
          next_state = STATE_B;
        end else begin
          next_state = STATE_C;
        end
      end

      STATE_B: begin
        // 根据输入信号决定下一个状态
        if (input_signal) begin
          next_state = STATE_C;
        end else begin
          next_state = STATE_A;
        end
      end

      STATE_C: begin
        // 根据输入信号决定下一个状态
        if (input_signal) begin
          next_state = STATE_A;
        end else begin
          next_state = STATE_B;
        end
      end
    endcase
  end

  // 根据当前状态生成输出信号
  assign output_signal = (current_state == STATE_B);

endmodule