将std_logic_vector的部分数组传递到实例化的端口映射中

entity ExampleModule is
  port (
    input_vector : in std_logic_vector(7 downto 0);
    output_vector : out std_logic_vector(3 downto 0)
  );
end entity ExampleModule;

architecture Behavioral of ExampleModule is
begin
  -- 在这里使用部分数组进行信号连接
  output_vector <= input_vector(7 downto 4);
end architecture Behavioral;

entity TopModule is
  port (
    input_vector : in std_logic_vector(7 downto 0);
    output_vector : out std_logic_vector(3 downto 0)
  );
end entity TopModule;

architecture Behavioral of TopModule is
  -- 实例化ExampleModule，并将部分数组传递给端口映射
  component ExampleModule is
    port (
      input_vector : in std_logic_vector(7 downto 0);
      output_vector : out std_logic_vector(3 downto 0)
    );
  end component;

begin
  -- 在这里进行ExampleModule的实例化，并传递部分数组给端口映射
  ExampleModule_inst : ExampleModule
    port map (
      input_vector => input_vector,
      output_vector => output_vector
    );
end architecture Behavioral;