我想在系统verilog的函数中反转并返回一个数组，我尝试了下面的代码，得到了以下错误

module test;

  function automatic logic [7:0] reverse_array(logic [7:0] input_array);
    logic [7:0] reversed_array;
    integer i;

    for (i = 0; i < 8; i = i + 1) begin
      reversed_array[i] = input_array[7 - i];
    end

    return reversed_array;
  endfunction

  initial begin
    logic [7:0] original_array;
    logic [7:0] result_array;

    original_array = 8'b01010101;

    result_array = reverse_array(original_array);

    $display("Original Array: %b", original_array);
    $display("Reversed Array: %b", result_array);
  end

endmodule