VHDL语言无约束std_logic_vector -递增/递减索引的检测

library ieee;
use ieee.std_logic_1164.all;

entity example is
end entity;

architecture rtl of example is
  signal my_vector : std_logic_vector(7 downto 0);
begin
  process
  begin
    -- 初始化向量
    my_vector <= "00000000";
    
    -- 递增索引的检测
    for i in my_vector'range-1 downto my_vector'low loop
      if my_vector(i) >= my_vector(i+1) then
        report "递增索引错误";
      end if;
    end loop;
    
    -- 递减索引的检测
    for i in my_vector'range-1 downto my_vector'low loop
      if my_vector(i) <= my_vector(i+1) then
        report "递减索引错误";
      end if;
    end loop;
    
    wait;
  end process;
end architecture;