VHDL实现分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clk_div IS
	PORT(clkin:IN STD_LOGIC;
		clkout:OUT STD_LOGIC);
END clk_div;
ARCHITECTURE clk_div_behavior OF clk_div IS
	SIGNAL counter:STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL temp:STD_LOGIC;
BEGIN
	PROCESS(clkin)
	BEGIN
		IF(clkin'EVENT AND clkin='1')THEN
			IF(counter="100")THEN        --注意，这里是0——4，一个周期1:1的高低电平
				counter<="000";
				temp<=NOT temp;
			ELSE
				counter<=counter+1;
			END	IF;
		END IF;
	END PROCESS;
	clkout<=temp;
END clk_div_behavior;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clk_div IS
	PORT(clk:IN STD_LOGIC;
		clk_div_2:OUT STD_LOGIC;
		clk_div_4:OUT STD_LOGIC;
		clk_div_8:OUT STD_LOGIC);
END clk_div;
ARCHITECTURE clk_div_behavior OF clk_div IS
SIGNAL counter:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'EVENT AND clk='1')THEN
			IF(counter="111")THEN
				counter="000";
			ELSE
				counter<=counter+1;
			END IF;
		END IF;
	END PROCESS;
	clk_div_2<=NOT counter(0);
	clk_div_4<=NOT counter(1);
	clk_div_8<=NOT counter(2);
END clk_div_behavior;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clk_div IS
	PORT(clk:IN STD_LOGIC;
		clk_div_6:OUT STD_LOGIC);
END	clk_div;
ARCHITECTURE clk_div_bahavior OF clk_div IS
	SIGNAL temp:STD_LOGIC_VECTOR(2 DOWNTO 0);
	CONSTANT counter:STD_LOGIC_VECTOR(2 DOWNTO 0):="101";
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'EVENT AND clk='1')THEN
			IF(temp=counter)THEN	--控制分频
				temp<="000";
			ELSE
				temp<=temp+1;
			END IF;
		END IF;
	END PROCESS;
	PROCESS(clk)
	BEGIN
		IF(clk'EVENT AND clk='1')THEN
			IF(temp="001")	--控制占空比
				clk_div_6<='1';
			ELSE
				clk_div_6<='0';
			END IF;
		END IF;
	END PROCESS;
END clk_div_bahavior;